Datasheet
Data Sheet 9 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
5 Electrical and Functional Description of Blocks
5.1 Power Supply
The TLE8102SG is supplied by power supply line V
DD
, used for the digital as well as the analog functions of the
device including the gate control of the power stages. A capacitor between pins V
DD
to GND is recommended.
The TLE8102SG can be programmed via SPI to enter sleep mode. In sleep mode, all outputs are turned off and
all dia
gnosis and biasing circuits are disabled. These actions reduce the quiescent current consumption from the
power supply. However, the SPI configuration registers (except for the channel on/off register) are not reset when
the TLE8102SG enters sleep mode. To exit sleep mode, a wake up command must be sent via SPI.
V
DD
= 4.5 V to 5.5 V, T
j
= -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Supply Voltage
V
DD
4.5 – 5.5 V –
Supply Current
I
VDD
– – 5 mA –
Supply Current in Sleep Mode
I
VDD(sleep)
– – 10 μA –
Wake up Time (after sleep mode)
1)
1) Not subject to production test, specified by design.
t
wake
– – 100 μs –
5.2 Parallel Inputs
There are two input pins available on the TLE8102SG to control the output stages.
Each input signal controls the output sta
ges of its assigned channel. For example, IN1 controls OUT1 and IN2
controls OUT2. Please refer to Figure 5 for details. The input pins are active
high and each have an integrated
pull-down current source. A comparator with hystere
sis determines the state of the signal on INn. The zener diode
protects the input circuit against ESD pulses.
The BOL
bit can be set via SPI. This bit determines if the output is exclusively controlled by the INn signals,
exclusively controlled by the corresponding data bits CHn
IN
or by a Boolean OR or AND operation of the two
inputs. The default setting of the BOL bits
programs the outputs to be controlled exclusively by the INn signals.
The SLEn bit can b
e set via SPI. This bit sets the slew rate of its assigned channel by selecting either slew rate 1
or slew rate 2. The slew rate also changes the over load switch off delay time (only for current limit 2).
channel 2
channel 1
&
OR
IN1
I
IN1
CH1
IN
BOL
gate
control
SLE1
IN
SPI
Figure 5 Input Control and Boolean Operator
Electrical Characteristics: Power Supply
5.1.1
5.1.2
5.1.3
5.1.4