Datasheet

Data Sheet 25 V1.5, 2012-08-17
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
5.6.3 SO High State Output Voltage V
SOH
V
DD
-
0.4
– – V I
SOH
= 2 mA
5.6.4 SO Low State Output Voltage V
SOL
– – 0.4 V I
SOL
= 2.5 mA
5.6.5 Serial Clock Frequency
(depending on SO load)
f
SCK
DC – 5 MHz –
5.6.6 Serial Clock Period (1/f
sclk
) t
p(SCK)
200 – – ns –
5.6.7 Serial Clock High Time t
SCKH
80 – – ns –
5.6.8 Serial Clock Low Time t
SCKL
80 – – ns –
5.6.9 Enable Lead Time (falling edge of
CS to rising edge of SCLK)
t
lead
200 – – ns –
5.6.10 Enable Lag Time (falling edge of
SCLK to rising edge of
CS)
t
lag
200 – – ns –
5.6.11 Data Setup Time (required time SI
to falling of SCLK)
t
SU
20 – – ns –
5.6.12 Data Hold Time (falling edge of
SCLK to SI)
t
H
20 – – ns –
5.6.13 Disable Time
1)
t
DIS
– – 150 ns –
5.6.14 Transfer Delay Time
2)
(CS high time
between two accesses)
t
dt
300 – – ns –
5.6.15 Data Valid Time t
valid
–
–
–
–
120
150
ns C
L
= 50 pF
1)
C
L
= 100 pF
1)
1) Not subject to production test, specified by design.
2) This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay time has
to be extended to the maximum fault delay time
t
d(fault)max
= 200 μs.
Electrical Characteristics: SPI Interface (cont’d)
V
DD
= 4.5 V to 5.5 V, T
j
= -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.