Datasheet
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 24 V1.5, 2012-08-17
SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance
state until the
CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Section 6 for further information.
5.6.2 Daisy Chain Capability
The SPI of TLE8102SG is daisy chain capable. In this configuration several devices are activated by the same
signal
CS. The SI line of one device is connected with the SO line of another device (see Figure 20), which builds
a chain. The ends of the chain are connected with the o
utput and input of the master device, SO and SI
respectively. The master device provides the master clock SCLK, which is connected to the SCLK line of each
device in the chain.
SI
device 1
SPI
SCLK
SO
CS
SI
device 2
SPI
SCLK
SO
CS
SI
device 3
SPI
SCLK
SO
CS
SO
SI
CS
SCLK
Figure 20 Daisy Chain Configuration
In the SPI block of each device, there is one shift register
where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the
CS line must go high to make the device accept the transferred data. In daisy chain
configuration the data shifted out at device 1 has been shifted in to device 2. When using three TLE8102SG
devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the
CS line must go
high (see Figure 21).
SI
SO
CS
CLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
time
Figure 21 Data Transfer in Daisy Chain Configuration
Electrical Characteristics: SPI Interface
V
DD
= 4.5 V to 5.5 V, T
j
= -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.6.1 Input Pull-down Current (SI, SCLK)
I
IN(SI,SCLK)
10 20 50 μA –
5.6.2 Input Pull-up Current (
CS) I
IN(CS)
10 20 50 μA –