Datasheet

V
DD
= 4.5 V to 5.5 V, T
j
= -40 ⋅C to +150 ⋅C, (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Input Low Voltage
V
INL
– – 1.0 V –
Input High Voltage
V
INH
2.0 – – V –
Input Voltage Hysteresis
1)
1) Not subject to production test, specified by design.
V
INHys
100 200 400 mV –
Input Pull-down Current
(IN1 to IN2)
I
IN(1 … 2)
20 50 100 μA –
TLE 8102 SG
Smart Dual Channel Powertrain Switch
Electrical and Functional Description of Blocks
Data Sheet 10 V1.5, 2012-08-17
5.3 Power Outputs
5.3.1 Timing Diagrams
The power transistors are switched on and off with a dedicated slope either via the parallel inputs or by
the CHn
IN
bits of the serial peripheral interface SPI. The switching times t
ON
and t
OFF
are designed equally. The
switching time of each channel can be selected via SPI by programming the SLEn bit of the desired output. See
Figure 6 for details
CS
V
DS
t
t
ON
t
OFF
t
20%
80%
SPI: ON SPI: OFF
Figure 6 Switching a Resistive Load
5.3.2 Inductive Output Clamp
When switching off inductive loads, the potential at pin OUT rises to V
DS(CL)
, as the inductance continues to drive
current. The inductive output clamp is necessary to prevent destruction of the device. See Figure 7 for details.
The maximum allowed load
inductance and current, however, are limited.
V
bat
I
D
V
DS(CL)
OUT
V
DS
GND
L,
R
L
Figure 7 Inductive Output Clamp
Electrical Characteristics: Parallel Inputs
5.2.1
5.2.2
5.2.3
5.2.4