Datasheet

TLE 7469
Data Sheet 15 Rev. 1.6, 2008-01-22
Circuit Description
Power On Reset
In order to avoid any system failure, a sequence of several conditions has to be passed.
When the level of
V
Q2
reaches the reset threshold V
RT
, the signal at RO remains LOW
for the Power-up reset delay time T
RD
. Then a second comparator checks whether
V
Q1
≥ V
RT1
and only if this test is passed the reset output is switched to HIGH. The Reset
output is only released (set to High level) if both output voltages have passed their
specific reset threshold
V
RT1/2
. The reset function and timing is illustrated in Figure 5.
The reset reaction time T
RR
avoids wrong triggering caused by short “glitches” on the
V
Q2
-line. For power-fail, in case of V
Q2
or V
Q1
power down (V
Q2
< V
RT2
or V
Q1
< V
RT1
for
t >T
RR
) a logic LOW signal is generated at the pin RO to reset an external
microcontroller.