Datasheet

Data Sheet 8 Rev. 1.1, 2009-01-19
TLE 7241E
Pin Configuration
Note: If a channel is unused, the OUTx, NEGx, and POSx pins should be connected
together.
8 SCK SPI Clock; Digital input pin. 3.3V and 5.0V logic
compatible
9 CSB Chip Select Bar; Active low digital input pin. 3.3V and
5.0V logic compatible
10 SI Serial Data Input; 3.3V and 5.0V logic compatible
11 V
SO
SPI Supply Voltage; connect a ceramic capacitor to GND
near the device
12 SO Serial Data Output; Supplied by Vso pin
13 TEST Test Pin; connect to GND
14 REF Voltage Reference; connect to external 2.5 V reference,
or connect to GND to enable internal reference.
15 GND Ground; signal ground
16 BAT BAT Input; connect to the solenoid supply voltage
through a series resistor. Connect a ceramic capacitor to
GND near the device
17 POS2 Positive Sense Pin Channel 2; connect to positive
terminal of external sense resistor with dedicated trace
18 NEG2 Negative Sense Pin Channel 2; connect to negative
terminal of external sense resistor with dedicated trace
19 OUT2 Output Channel 2; Drain of Output DMOS; connect to
negative terminal of external sense resistor
20 PGND2 Power Ground Channel 2; internally connected to
PGND1
Expose
d Lead
Frame
EPGND GND; Should be connected to GND, PGND1 and PGND2
and to the ground plane of the ECU
Pin Definitions and Functions (cont’d)
Pin Pin Name Pin Description