Datasheet

TLE 6209 R
Data Sheet, Version 3.1 24 2007-08-01
Figure 6 Output Delay and Switching Time Definitions
Figure 7 Standard Data Transfer Timing
90%
10%
t
d1
t
RISE
t
FALL
50% 50%
t
d2
V
OUT
PWM
Input
0
5
V
10%
90%
100%
DIR = L / H => V
OUT
= V
OUT 1/2
Resistive load to Vs =>
t
RISE
= t
RISE L
, t
FALL
= t
FALL L
t
d1
= t
d OFF L
, t
d2
= t
d ON L
Resistive load to GND =>
t
RISE
= t
RISE H
, t
FALL
= t
FALL H
t
d1
= t
d ON H
, t
d2
= t
d OFF H
3
0 732
4
1
SDI
SCLK
CSN
0 765432
1
SDO
CSN High to Low & rising edge of SCLK: SDO is enabled. Status information is transfered to Output Shift Register
CSN Low to High: Data from Shift-Register is transfered to Output Driver Logic
previous Status
actual Data
SDI: Data will be accepted on the falling edge of CLK-Signal
SDO: State will change on the rising edge of CLK-Signal
__ ______
time
0
0
0
+
new Data
actual Status
actual Dataold Data
1
20 7654
56