Datasheet

TLE 6209 R
Data Sheet, Version 3.1 21 2007-08-01
Serial Data Input Timing
Serial Clock period
t
PSCLK
500 – –ns–
Serial Clock high time
t
SCLKH
250 – –ns–
Serial Clock low time
t
SCLKL
250 – –ns–
Serial Clock low
before CSN low
t
bef
250 – –ns–
CSN setup time
t
lead
250 – –ns–
SCLK setup time
t
lag
250 – –ns–
Clock low after CSN high
t
beh
250 – –ns–
SDI setup time
t
SDISU
125 – –ns–
SDI hold time
t
SDIHO
125 – –ns–
Input signal rise time
at pin SDI, SCLK and CSN
t
rSIN
– –100ns–
Input signal fall time
at pin SDI, SCLK and CSN
t
fSIN
– –100ns–
Serial Data Output Timing
SDO rise time
t
rSDO
– 2550nsC
L
= 100 pF
SDO fall time
t
fSDO
– 2550nsC
L
= 100 pF
SDO enable time
t
ENSDO
– – 125 ns low impedance
SDO disable time
t
DISSDO
– – 125 ns high impedance
SDO valid time
t
VASDO
–50125nsV
DO
< 0.2 V
CC
;
V
DO
> 0.7 V
CC
;
C
L
= 100 pF
3.3 Electrical Characteristics (cont’d)
8 V <
V
S
< 40 V; 4.75 V < V
CC
< 5.25 V; INH = High; all outputs open;
– 40 °C <
T
j
< 150 °C; unless otherwise specified
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.