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PG-DSO-20-37

7 A H-Bridge for DC-Motor Applications

Data Sheet

TLE 6209 R

Data Sheet, Rev.3.1 1 2007-08-01

1Overview

1.1 Features

• Delivers up to 6 A continuous and 7 A peak current

• Optimized for DC motor management applications

•Very low

DS ON

of typ. 150 mΩ @25°C per switch

• Operates at supply voltages of up to 40V

• Overvoltage Protection against transients up to 45 V

• Outputs fully short circuit protected

• Standard SPI-Interface, daisy chain capability

• Adjustable chopper current regulation of up to 7 A

• Temperature monitor with prewarning, warning and shutdown

• Over- and Undervoltage-Lockout

• Open load detection

• Detailed load failure diagnosis by SPI

• Minimized power dissipation due to active free-wheeling

• Low EMI due to voltage slope regulation

• Very low current consumption (typ. 20 µA @ 25 °C) in stand-by (Inhibit) mode

• Enhanced power PG-DSO-Package

• Green Product (RoHS compliant)

• AEC Qualified

Functional Description

The TLE 6209 R is an integrated power H-Bridge with D-MOS output stages for driving

bidirectional loads such as DC-Motors. The design is based on Infineons Smart Power

Technology SPT which allows bipolar, CMOS and power D-MOS devices on the same

monolithic circuit.

Operation modes forward (cw), reverse (ccw) and brake are invoked by two control pins

PWM and DIR. Protection and a reliable diagnosis of overcurrent, openload, short-circuit

to ground, to the supply voltage or across the load are integrated. Detailed diagnostic

Type Package

TLE 6209 R PG-DSO-20-37

Summary of content (30 pages)

PAGE 1
7 A H-Bridge for DC-Motor Applications TLE 6209 R Data Sheet 1 Overview 1.1 Features • • • • • • • • • • • • • • • • • • Delivers up to 6 A continuous and 7 A peak current Optimized for DC motor management applications Very low RDS ON of typ.
PAGE 2
TLE 6209 R information is given via the 8 bit SPI status word. An integrated chopper current limitation limits the current e.g. to reduce power dissipation during mechanical block of a DC motor. Several device parameters can be set by the SPI control word. A three-level temperature monitoring with prewarning, warning and shutdown is included for controlled operation under critical power loss conditions.
PAGE 3
TLE 6209 R 1.2.1 Pin Definitions and Functions Pin No. Symbol Function 1, 10, 11, 20 GND Ground; internally connected to cooling tab (heat slug); to reduce thermal resistance place cooling areas and thermal vias on PCB. 2,3 OUT1 Output 1; output of D-MOS half bridge 1; external connection between pin 2 and pin 3 is necessary.
PAGE 4
TLE 6209 R 1.2.1 Pin Definitions and Functions (cont’d) Pin No. Symbol Function 16 DRV Drive; Input for external charge pump capacitor CDRV 18,19 OUT2 Output 2; output of D-MOS half bridge 2; external connection between pin 2 and pin 3 is necessary. 1.
PAGE 5
TLE 6209 R 2 Circuit Description 2.1 Serial Peripheral Interface (SPI) The SPI is used for bidirectional communication with a control unit. The 8-bit programming word or control word (see Table 1) is read in via the SDI serial data input, and this is synchronized with the serial clock input SCLK. The status word appears synchronously at the SDO serial data output (see Table 4). The transmission cycle begins when the chip is selected with the chip-select-not (CSN) input (H to L).
PAGE 6
TLE 6209 R Table 2 Programmable Chopper Current Limit IL_xx Bit 1 Bit 0 Current limit 0 0 0 1 1 0 1 1 IL_00 IL_01 IL_10 IL_11 Note: For actual values, see page 16 Table 3 Programmable Chopper OFF-time tOFF_xx Bit 4 Bit 3 Chopper-OFF-time 0 0 0 1 1 0 1 1 tOFF_00 tOFF_01 tOFF_10 tOFF_11 Note: For actual values, see page 16 Table 4 Diagnosis Data Protocol Bit H = Error/L = no error 7 Power supply fail 6 not used, always H 5 Short to VS or across the load 4 Short to GND
PAGE 7
TLE 6209 R Table 5 Temperature Monitoring Bit 2 Bit 1 Chip Temperature 1 0 Temperature Warning 1 1 Overtemperature Shutdown 2.2 Supply 2.2.1 Logic Supply Voltage, Power-On-Reset The logic is supplied with 5 V by the VCC pin, separated from the power stage supply VS. The advantage of this system is that information stored in the logic remains intact even in the event of failures in the supply voltage VS. The power supply failure information can be read out via the SPI.
PAGE 8
TLE 6209 R 2.3.3 Direction and PWM The power stages are controlled by the direct inputs DIR and PWM as given in Table 6 and further illustrated in Figure 2. The DIR input gives the direction of output current, while the PWM input controls whether the current is increased or reduced. The SPI control bit 2 sets the decay mode, i.e. determines what happens if PWM = L.
PAGE 9
TLE 6209 R 2.4 Power Stages The output stages consist of a DMOS H-bridge built by two highside switches and two lowside switches. Integrated circuits protect the outputs against overcurrent and overtemperature if there is a short-circuit to ground or to the supply voltage or across the load. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. 2.4.
PAGE 10
TLE 6209 R 2.5 Protection and Diagnosis 2.5.1 Short of Output to Ground The high-side switches are protected against a short of the output to ground by an over current shutdown. If a high-side switch is turned on and the current rises above the highside shutdown threshold ISDH for longer than the shutdown delay time tdOC, all output transistors are turned off and bit 4 the SPI diagnosis word is set. During the delay time, the current is limited to ISC (typically 20 A).
PAGE 11
TLE 6209 R thresholds. As soon as a threshold is reached, the according status bits are set in the SPI diagnosis word (c.f. Table 5). If the overtemperature shutdown threshold is reached, the output stages are turned off. The temperature monitoring messages and the over temperature shutdown are latched and can be reset by the status register reset bit 7 of the SPI control word or a POR. 2.5.
PAGE 12
TLE 6209 R 3 Characteristics 3.1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. VS VS VCC VI – 0.3 40 V – –1 45 V – 0.3 5.5 V – 0.3 5.5 V t < 0.5 s; IS > – 2 A 0 V < VS < 40 V 0 V < VS < 40 V 0 V < VCC < 5.5 V Logic output voltage (SDO) VO – 0.3 5.5 V 0 V < VS < 40 V 0 V < VCC < 5.5 V Output voltage (OUT1, OUT2) VOUT – 0.3 V VS + 1,5V – 0 V < VS < 40 V Charge pump buffer voltage (DRV) VDRV VS – VS + – 0 V < VS < 40 V 0.
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TLE 6209 R 3.2 Operating Range Parameter Symbol Limit Values min. Unit Remarks max. Supply voltage VS VUV OFF 40 V After VS rising above VUV ON Supply voltage slew rate dVS /dt –10 10 V/µs – Logic supply voltage VCC VS VS VI 4.75 5.50 V – – 0.3 Outputs in tristate – 0.3 VUV ON V VUV OFF V VCC V fCLK Tj – 2 MHz – – 40 150 °C – Junction pin RthjC – 1.
PAGE 14
TLE 6209 R 3.3 Electrical Characteristics 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Conditions Current Consumption Quiescent current IS – – 50 µA INH = Low; VS = 13.2 V Quiescent current IS – 10 30 µA INH = Low; VS = 13.2 V; Tj = 25 °C Logic-Supply current ICC ICC IS – – 20 µA INH = Low – 2.0 4.0 mA – – 2.8 5.0 mA – – 5.4 5.7 V 4.
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TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. Unit Test Conditions typ. max. 140 170 mΩ 5.2 V < VS < 40 V Tj = 25 °C; CDRV = 33 nF – 280 mΩ 5.2 V < VS < 40 V CDRV = 33 nF 130 160 mΩ 5.2 V < VS < 40 V Tj = 25 °C; CDRV = 33 nF – 270 mΩ 5.2 V < VS < 40 V CDRV = 33 nF – 1.0 1.5 V – 1.0 1.
PAGE 16
TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Conditions min. typ. max. IOCD tdOC 30 – 130 mA – 2 – 8 ms – Current limit IL_00 3.4 4 4.6 A Bit 0 = L; Bit 1 = L; Current limit IL_01 4.25 5 5.75 A Bit 0 = H; Bit 1 = L; Current limit IL_10 5.1 6 6.9 A Bit 0 = L; Bit 1 = H; Current limit IL_11 5.95 7 8.
PAGE 17
TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. Unit Test Conditions High-Side Switch Overcurrent High-side shutdown threshold ISDH 8 12 18 A – Shutdown delay time tdSD ISC 15 25 40 µs – – – 25 A during tdSD Short circuit current Note: For short circuit current definition, see Figure 5.
PAGE 18
TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. max. – – 0.7 0.
PAGE 19
TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. Unit Test Conditions max. SPI-Interface Delay Time from Stand-by to Data In/Power on Reset – – 100 µs – – – 0.7 – 0.2 – – VCC VCC 50 300 500 mV – – 50 – 25 – 10 µA VCSN = 0.7 × VCC – 50 – – µA VCSN = 0.
PAGE 20
TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Conditions min. typ. max. VCC VCC – V ISDOH = 1 mA –1.0 –0.85 – 0.25 0.4 V Tri-state leakage current VSDOL ISDOLK – 10 – 10 µA Tri-state input capacitance CSDO – 10 15 pF ISDOL = – 1.6 mA VCSN = VCC 0 V < VSDO < VCC VCSN = VCC 0 V < VCC < 5.
PAGE 21
TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Conditions min. typ. max.
PAGE 22
TLE 6209 R 3.3 Electrical Characteristics (cont’d) 8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; – 40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values min. typ. Unit Test Conditions max.
PAGE 23
TLE 6209 R 4 Diagrams V 13.2V 9V 9V VOUT 0 tOFF_xx IOUT Figure 4 Switch-OFF time during current limitation (chopper OFF-time) Vs V Vs 5V PWM 0 OUT tdSD IOUT ISDH ISC GND Figure 5 Short circuit of high-side switch to GND Data Sheet, Version 3.
PAGE 24
TLE 6209 R V 5 PW M Input 50% 50% 0 t R ISE t FALL 100% 90% 90% V O UT 10% 10% t d1 td2 DIR = L / H => V O UT = V O UT 1/2 Resistive load to V s => t R ISE = t RISE L , t FALL = t FAL L L t d1 = t d O FF L , t d2 = t d O N L Figure 6 Resistive load to G ND => t R IS E = t R ISE H, t FALL = t FALL H t d1 = t d O N H, t d2 = t d O FF H Output Delay and Switching Time Definitions CSN High to Low & rising edge of SCLK: SDO is enabled.
PAGE 25
TLE 6209 R CSN High to Low & SCLK stays Low: Status information of Data Bit 0 ( Error Flag ) is transfered to SDO CSN time SCLK SDI SDI: Data is not accepted SDO tristate _ 0 tristate SDO: Status information of Data Bit 0 ( Error-Flag ) will stay as long as CSN is low Figure 8 Timing for Error Detection Only 0.7 VCC CSN 0.2 VCC tSCLKH 0.7 VCC SCLK 0.2 VCC tlead tbef tSCLKL tlag tSDISU tbeh tSDIHO SDI Don´t care Don´t care Valid 0.7 VCC Valid Don´t care 0.
PAGE 26
TLE 6209 R trSIN tfSIN 0.7 VCC SCLK 50 % 0.2 VCC trSDO 0.7 VCC SDO ( low to high ) 0.2 VCC tVASDO tfSDO 0.7 VCC SDO Figure 10 ( high to low ) 0.2 VCC DO Valid Data Delay Time and Valid Time tfSIN trSIN 0.7 VCC CSN 50 % 0.2 VCC tENSDO tDISSDO 10 kΩ Pullup to VCC SDO tENSDO tDISSDO 10 kΩ Pulldown 50 % to GND SDO Figure 11 50 % SDO Enable and Disable Time Data Sheet, Version 3.
PAGE 27
TLE 6209 R 5 Application Watchdog Reset Q TLE 4278G Z39 D CQ 22µF Vbat I CD 10nF 100µF 100nF GND CDRV WD R VCC VCC DRV 15 MicroController for EMS/ETC Function INH 9 DIS 12 CSN SDI SCLK SDO PWM DIR Bias Charge Pump Inhibit FaultDetect 4,17 8 2,3 6 S 5 P 7 I OUT 1 Driver 8 Bit Logic and Latch & 18,19 Gate-Control OUT 2 M 14 Direct Input 13 UV GND OV Micro-Controller for Evaluation Process Monitoring ≥1 TSD GND GND Figure 12 VS 33nF 16 Application Circu
PAGE 28
TLE 6209 R 6 Package Outlines B 5˚ ±3˚ 0.02 0.25 +0.0 7 - 1.3 1.2 -0.3 11 ±0.15 1) 2.8 3.5 max. 0 +0.15 3.25 ±0.1 PG-DSO-20-37 (Plastic Dual Small Outline Package) 15.74 ±0.1 1.27 0.4 Index Marking 6.3 0.1 +0.13 0.25 M 20 11 1 1 x 45˚ 10 A 20x 14.2 ±0.3 Heatsink 0.95 ±0.15 0.25 M B 15.9 ±0.15 1) A 1) Does not include plastic or metal protrusion of 0.15 max.
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TLE 6209 R 7 Revision History Version Date Rev. 3.
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Edition 2007-08-01 Published by Infineon Technologies AG 81726 Munich, Germany © 8/1/07 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.