Datasheet

TLE 4729 G
Data Sheet 9 2005-01-17
Diagrams
Timing between IXX and Phase X to prevent setting the error flag
Operating conditions:
+
V
S
= 14 V, T
j
= 25 °C, I
err
= 1 mA, load = 3.3 mH, 1 Ω
If
t
PI
< typ. 5 µs, an error “open load” will be set.
If
t
IP
< typ. 12 µs, an error “open load” will be set.
t
PI
AET02197
Phase X
XX
Ι
a)
t
IP
Phase X
XX
Ι
AET02198
b)