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Data Sheet 1 2005-01-17

2-Phase Stepper-Motor Driver

Bipolar-IC

TLE 4729 G

Features

•2 × 0.7 amp. full bridge outputs

• Integrated driver, control logic and current control

(chopper)

• Very low current consumption in inhibit mode

• Fast free-wheeling diodes

• Max. supply voltage 45 V

• Output stages are free of crossover current

• Offset-phase turn-ON of output stages

• All outputs short-circuit proof

• Error-flag for overload, open load, over-temperature

• SMD package P-DSO-24-9

Functional Description

TLE 4729 G is a bipolar, monolithic IC for driving bipolar stepper motors, DC motors and

other inductive loads that operate by constant current. It is fully pin and function

compatible except the current programming is inverse to the TLE 4728 G with an

additional inhibit feature. The control logic and power output stages for two bipolar

windings are integrated on a single chip which permits switched current control of motors

with 0.7 A per phase at operating voltages up to 16 V.

The direction and value of current are programmable for each phase via separate control

inputs. In the case of low at all four current program inputs the device is switched to

inhibit mode automatically. A common oscillator generates the timing for the current

control and turn-on with phase offset of the two output stages. The two output stages in

full-bridge configuration include fast integrated freewheeling diodes and are free of

crossover current. The device can be driven directly by a microprocessor in several

modes by programming phase direction and current control of each bridge

independently.

Type Ordering Code Package

TLE 4729 G on request P-DSO-24-9 (SMD)

Summary of content (27 pages)

PAGE 1
2-Phase Stepper-Motor Driver Bipolar-IC TLE 4729 G Features • 2 × 0.7 amp. full bridge outputs • Integrated driver, control logic and current control (chopper) • Very low current consumption in inhibit mode • Fast free-wheeling diodes • Max.
PAGE 2
TLE 4729 G With the two error outputs the TLE 4729 G signals malfunction of the device. Setting the control inputs low resets the error flag and by reactivating the bridges one by one the location of the error can be found.
PAGE 3
TLE 4729 G Pin Definitions and Functions Pin Function 1, 2, 23, 24 Digital control inputs IX0, IX1 for the magnitude of the current of the particular phase. Iset = 450 mA with Rsense = 1 Ω IX1 IX0 Phase Current Example of Motor Status L L 0 No current1) L H 0.155 × Iset Hold H L Iset Normal mode H H 1.
PAGE 4
TLE 4729 G Block Diagram +V S OSC Oscillator C OSC T11 T12 D11 Ι 10 Ι 11 Phase 1 Error 1 Function Logic D12 T13 T14 D13 Q11 Q12 D14 Phase 1 R1 R sense Error-Flag Generation Error 2 TLE 4729 G +V S Inhibit T21 T22 D21 Ι 20 Ι 21 Phase 2 Function Logic D22 T23 T24 D23 Q21 Q22 D24 Phase 2 R2 GND R sense AEB02196 Figure 2 Data Sheet 4 2005-01-17
PAGE 5
TLE 4729 G Absolute Maximum Ratings Tj = – 40 to 150 °C Parameter Supply voltage Error outputs Output current Ground current Logic inputs Oscillator voltage R1, R2 input voltage Junction temperature Storage temperature Symbol Limit Values Unit Remarks min. max. – 0.3 45 V – – 0.3 – 45 3 V mA – – –1 1 A – –2 – A – – 15 15 V IXX; Phase 1, 2 – 0.3 6 V – – 0.
PAGE 6
TLE 4729 G Characteristics VS = 6 to 16 V; Tj = – 40 to 130 °C Parameter Symbol Limit Values min. typ. max. Unit Test Condition Current Consumption From + VS IS – – 50 µA From + VS IS 20 30 50 mA IOSC VOSCL VOSCH fOSC 90 0.8 1.7 18 120 1.3 2.3 24 150 1.9 2.9 30 µA V V kHz – – – IQ – 0 – mA IX0 = L; IX1 = L Vch Vcs Vca 40 410 630 70 450 700 100 510 800 mV mV mV IX0 = H; IX1 = L IX0 = L; IX1 = H IX0 = H; IX1 = H VI VIHy IIL IIL IIH 1.2 – – 10 – 100 –1 1.
PAGE 7
TLE 4729 G Characteristics (cont’d) VS = 6 to 16 V; Tj = – 40 to 130 °C Parameter Symbol Limit Values Unit Test Condition min. typ. max. VErrSat IErrL 50 – 200 – 500 10 mV µA IErr = 1 mA VErr = 25 V Tjsd Tjpa ∆Tj Tjsdhy Tjpahy 140 120 10 – – 150 130 20 20 20 160 140 30 – – °C °C K K K IQ1, 2 = 0 A VErr = L ∆Tj = Tjsd – Tjpa 0.3 0.5 1000 0.9 1.0 0.5 0.8 1500 1.2 1.3 V V µA V V IQ = – 0.45 A IQ = – 0.7 A VS = VQ = 40 V IQ = 0.45 A IQ = 0.7 A 1.0 0.3 1.2 0.6 V V IQ = 0.
PAGE 8
TLE 4729 G Characteristics (cont’d) VS = 6 to 16 V; Tj = – 40 to 130 °C Parameter Symbol Limit Values min. typ. max. – – – – – – – 5 12 45 15 30 3 1 20 100 100 50 80 10 5 Unit Test Condition Error Output Timing Time Phase X to IXX Time IXX to Phase X Delay Phase X to Error 2 Delay Phase X to Error 1 Delay IXX to Error 2 Reset delay after Phase X Reset delay after IXX tPI tIP tPEsc tPEol tIEsc tRP tRI µs µs µs µs µs µs µs – For details see next four pages.
PAGE 9
TLE 4729 G Diagrams Timing between IXX and Phase X to prevent setting the error flag Operating conditions: + VS = 14 V, Tj = 25 °C, Ierr = 1 mA, load = 3.3 mH, 1 Ω a) Ι XX Phase X t PI AET02197 If tPI < typ. 5 µs, an error “open load” will be set. b) Ι XX Phase X t IP AET02198 If tIP < typ. 12 µs, an error “open load” will be set.
PAGE 10
TLE 4729 G This time strongly depends on + VS and inductivity of the load, see diagram below. Time tIP vs. Load Inductivity AED02199 30 t IP µs 25 VS= 6 V 20 15 10 9V 12 V 16 V 5 0 0 10 20 30 40 mH L 60 Propagation Delay of the Error Flag Operating conditions: + VS = 14 V, Tj = 25 °C, Ierr = 1 mA, load = 3.3 mH, 1 Ω a) IXX = H, error condition: short circuit to GND. Phase X Error 2 t PEsc AED02200 typ.
PAGE 11
TLE 4729 G b) IXX = H, error condition: open load (equivalent: short circuit to + VS). Phase X Error 1 t PEol AET02201 typ. tPEol: 15 µs c) Phase X = H or L, const.; error condition: short circuit to GND. Ι XX Error 2 t IEsc AET02202 typ. tIEsc: 30 µs tIEsc is also measured under the condition: begin of short circuit to GND till error flag set.
PAGE 12
TLE 4729 G d) IXX = H, reset of error flag when error condition is not true. Phase x Error X t RP AET02203 typ. tRP: 3 µs e) Phase X = H or L, const.; reset of error flag when error condition is not true. Ι XX Error X t RI AET02204 typ.
PAGE 13
TLE 4729 G Quiescent Current IS vs. Supply Voltage VS; bridges not chopping; Tj = 25 °C AED02205 60 ΙS Quiesc. Current IS vs. Junct. Temp. Tj; bridges not chopping, VS = 14 V mA Ι QX = 50 0.70 A AED02206 60 Ι QX = 0.70 A mA ΙS 50 0.45 A 0.45 A 40 40 0.07 A 0.07 A 30 30 20 20 10 10 0 -50 0 5 10 15 V 20 0 50 VS Oscillator Frequency fOsc vs. Junction Temperature Tj Output Current IQX vs.
PAGE 14
TLE 4729 G Output Saturation Voltages Vsat vs. Output Current IQ Forward Current IF of Free-Wheeling Diodes vs. Forward Voltages VF AED02209 2.0 V sat ΙF V S = 14 V T j = 25 C V A T j = 25 ˚C V Fl V Fu 0.8 1.5 0.6 V satuC 1.0 AED02210 1.0 0.4 V satl V satuD 0.5 0.2 0 0 0.2 0.4 0 0.6 A 0.8 ΙQ C OSC TC 3 V 1.5 AED02212 16 P tot L phase x = 10 mH R phase x = 2 Ω W 1.0 Permissible Power Dissipation Ptot vs. Case Temp. TC (measured at pin 5) AED02211 P tot 0.
PAGE 15
TLE 4729 G Input Characteristics of IXX, Phase X i Ι xx Output Leakage Current AED02213 40 µA 20 AED02214 1.2 Ι xx ΙR mA 0.8 0 V S = 40 V Phase X -20 0.4 V S = 16 V -40 Tj = -60 0 40 C 25 C 150 C -80 -0.4 -100 -120 -6 -0.8 -4 -2 0 2 4 V 6 V Ι xx 0 10 20 30 V VQ 40 Quiescent Current IS vs.
PAGE 16
TLE 4729 G +12V 100 nF 100 µ F 11 VS 1 Ι 10 2 Ι 11 3 21 Microcontroller 14 24 Q11 Phase 1 Error 1 Error 2 Q12 TLE 4729 G Ι 20 23 Ι 21 22 Phase 2 OSC 4 22 nF Q21 Q22 15 R2 1Ω 9 12 16 13 M Stepper Motor GND 10 5,6,7,8, 17,18,19,20 R1 1Ω AES02216 Figure 3 Data Sheet Application Circuit 16 2005-01-17
PAGE 17
TLE 4729 G 100 µF VS 100 nF ΙS +V S ΙΙ Ι Err VΙ V satu Ι XX, Phase X V Fu Ι Rl TLE 4729 G Output Error X Ι Ru ΙQ V satl Osc V Err GND Ι OSC V OSC R sense Ι SL Ι GND 2.
PAGE 18
TLE 4729 G full step operation normal mode accelerate mode Ι 10 H L Ι 11 H L t t H Phase 1 L t i acc i set Ι Q1 t - i set - i acc i acc i set Ι Q2 t - i set - i acc Phase 2 H L Ι 20 H L Ι 21 H L t t t AED02218 Figure 5 Data Sheet Full Step Operation 18 2005-01-17
PAGE 19
TLE 4729 G half step operation normal mode accelerate mode Ι 10 H L Ι 11 H L t t H Phase 1 L t i acc i set Ι Q1 t - i set - i acc i acc i set Ι Q2 t - i set - i acc Phase 2 H L Ι 20 H L Ι 21 H L t t t AED02219 Figure 6 Data Sheet Half Step Operation 19 2005-01-17
PAGE 20
TLE 4729 G V Osc V Osc H V Osc L t Ι Rsense 1 0 t Ι Rsense 2 0 t V Q12 + VS V FU V satl V ca 0 t V Q11 + VS V satu D V satu C V Q22 + VS 0 V Q21 + VS t Ι Q1 i acc Ι Q2 t i acc t Operating conditions: VS = 14 V L phase x = 10 mH R phase x = 4 Ω Figure 7 Data Sheet Phase x = H =H Ι XX AED02220 Current Control in Chop-Mode 20 2005-01-17
PAGE 21
TLE 4729 G V Osc 2.3 V 1.3 V 0V Oscillator High Imped.
PAGE 22
TLE 4729 G Calculation of Power Dissipation The total power dissipation Ptot is made up of Saturation losses Psat (transistor saturation voltage and diode forward voltages), Quiescent losses Pq (quiescent current times supply voltage) and Switching losses Ps (turn-ON / turn-OFF operations). The following equations give the power dissipation for chopper operation without phase reversal. This is the worst case, because full current flows for the entire time and switching losses occur in addition.
PAGE 23
TLE 4729 G +V S Tx1 Dx1 Dx2 Tx2 L Tx3 Dx3 Dx4 Tx4 VC R sense AET02222 Figure 9 Turn-ON Turn-OFF ΙN iR Voltage and Current on Chopper Transistor iD V S + V Fu V S + V Fu V satl t D ON t ON t D OFF t OFF tP Figure 10 Data Sheet t AET02223 Voltage and Current on Chopper Transistor 23 2005-01-17
PAGE 24
TLE 4729 G Application Hints The TLE 4729 G is intended to drive both phases of a stepper motor. Special care has been taken to provide high efficiency, robustness and to minimize external components. Power Supply The TLE 4729 G will work with supply voltages ranging from 5 V to 16 V at pin VS. Surges exceeding 16 V at VS wont harm the circuit up to 45 V, but whole function is not guaranteed. As soon as the voltage drops below approximately 16 V the TLE 4729 G works promptly again.
PAGE 25
TLE 4729 G Application Hints (cont’d) Optimizing Noise Immunity Unused inputs should always be wired to proper voltage levels in order to obtain highest possible noise immunity. To prevent crossconduction of the output stages the TLE 4729 G uses a special break before make timing of the power transistors. This timing circuit can be triggered by short glitches (some hundred nanoseconds) at the phase inputs causing the output stage to become high resistive during some microseconds.
PAGE 26
TLE 4729 G Only in the case of a short circuit to GND, the most probably kind of a short circuit in automotive applications, the malfunction is signaled dominant (see d) in logic table) by a separate error flag. Simultaneously the output current is disabled after 30 µs to prevent disturbances. A phase change-over or putting both current control inputs of the affected bridge on low potential resets the error flipflop. Being a separate flipflop for every bridge, the error can be located in easy way.
PAGE 27
TLE 4729 G Package Outlines 1.27 8˚ MAX. 7.6 -0.2 1) +0.0 9 0.35 x 45˚ 0.23 2.65 MAX. 2.45 -0.2 0.2 -0.1 P-DSO-24-9 (Plastic Dual Small Outline Package) 0.4 +0.8 0.1 0.35 +0.15 2) 0.2 24x 24 1 10.3 ±0.3 13 15.6 -0.4 1) 12 Index Marking 1) 2) Does not include plastic or metal protrusion of 0.15 max. per side Lead width can be 0.61 max. in dambar area Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.