Datasheet

TLE42794
General Product Characteristics
Data Sheet 10 Rev. 1.1, 2008-10-09
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Value Unit Conditions
Min. Typ. Max.
TLE42794G (PG-DSO-8)
4.3.4 Junction to Soldering Point
1)
1) not subject to production test, specified by design
R
thJSP
– 80 – K/W measured to pin 5
4.3.5 Junction to Ambient
1)
R
thJA
–113–K/W
2)
2) Specified R
thJA
value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.6 – 172 – K/W Footprint only
3)
3) Specified R
thJA
value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm
3
board with 1 copper layer (1 x 70µm Cu).
4.3.7 – 142 – K/W 300mm
2
heatsink area on
PCB
3)
4.3.8 – 136 – K/W 600mm
2
heatsink area on
PCB
3)
TLE42794GM (PG-DSO-14)
4.3.9 Junction to Soldering Point
1)
R
thJSP
– 27 – K/W measured to group of pins
3, 4, 5, 10, 11, 12
4.3.10 Junction to Ambient
1)
R
thJA
–63–K/W
2)
4.3.11 – 104 – K/W Footprint only
3)
4.3.12 – 73 – K/W 300mm
2
heatsink area on
PCB
3)
4.3.13 – 65 – K/W 600mm
2
heatsink area on
PCB
3)
TLE42794E (PG-SSOP-14 exposed pad)
4.3.14 Junction to Case
1)
R
thJC
– 10 – K/W measured to Exposed
Pad
4.3.15 Junction to Ambient
1)
R
thJA
–47–K/W
2)
4.3.16 – 145 – K/W Footprint only
3)
4.3.17 – 63 – K/W 300mm
2
heatsink area on
PCB
3)
4.3.18 – 53 – K/W 600mm
2
heatsink area on
PCB
3)