Datasheet

Data Sheet 14 Rev. 1.4, 2007-02-19
TLE 4278 G
Watchdog Timing
The frequency of the watchdog pulses has to be higher than the minimum pulse
sequence which is set by the external reset delay capacitor
C
D
. Calculation can be done
according to the formulas given in Figure 8.
The watchdog output is internally connected to the output Q via a 30 kΩ pull-up resistor.
To generate a watchdog created reset signal for the microcontroller the pin WO can be
connected to the reset input of the microcontroller. It is also allowed to parallel the
watchdog out to the reset out.
Figure 8 Timing of the Watchdog Function
AED03099
W
V
V
V
Q
D
V
V
WO
V
DU
-V
DWL
() Ι (
D, wc
+
D, wd
) Ι
Ι
D, wc
Ι x
D, wd
T
WD, p
=
WD, L
t
WD, p
T
WI, tr
T
WD, L
t =
VV(
DU
-
DWL
)
Ι
D, wc
T =
VV(
DU
-
DWL
)
Ι
D, wd
DU
V
V
DWL
Ι
Ι
WI, tr
C
D
;;
D
C
D
C
t
t
t
t
t