Datasheet

Data Sheet 8 Rev. 1.7, 2007-02-19
TLE 4275
Figure 3 Test Circuit
Figure 4 Reset Timing
AES02472
D
V
I
D
C
47 nF
GND
RO
5 k Ω
V
Q
V
RO
D
V
D, d
I
100 nF
I
C
2
1000 µF
C
I 1
Q
22 µF
C
Q
R
ext
1
4
5
2
3
I
I I
Q
RO
I
GND
I
D, c
I
I
AED03010
Thermal
t
rd
Power-on-Reset Voltage Dip Secondary Overload
at OutputSpike
V
Ι
D,c
Ι
=
Vd
dt
V
Q
Q, rt
V
t
rr
<
rr
t
at Input
Undervoltage
Shutdown
C
D
t
V
RO
D
V
t
t
t
V
DU
V
DRL