Datasheet

TLE42754
General Product Characteristics
Data Sheet 9 Rev. 1.11, 2012-01-20
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Value Unit Conditions
Min. Typ. Max.
TLE42754D (PG-TO252-5)
4.3.4 Junction to Case
1)
1) not subject to production test, specified by design
R
thJC
–3.7–K/W–
4.3.5 Junction to Ambient
1)
R
thJA
–27–K/W
2)
2) Specified R
thJA
value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.6 – 110 – K/W footprint only
3)
3) Specified R
thJA
value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm
3
board with 1 copper layer (1 x 70µm Cu).
4.3.7 – 57 – K/W 300 mm
2
heatsink area
on PCB
3)
4.3.8 – 42 – K/W 600 mm
2
heatsink area
on PCB
3)
TLE42754G (PG-TO263-5)
4.3.9 Junction to Case
1)
R
thJC
–3.7–K/W–
4.3.10 Junction to Ambient
1)
R
thJA
–22–K/W
2)
4.3.11 – 70 – K/W footprint only
3)
4.3.12 – 42 – K/W 300 mm
2
heatsink area
on PCB
3)
4.3.13 – 33 – K/W 600 mm
2
heatsink area
on PCB
3)
TLE42754E (PG-SSOP-14 exposed pad)
4.3.14 Junction to Case
1)
R
thJC
–7–K/W–
4.3.15 Junction to Ambient
1)
R
thJA
–43–K/W
2)
4.3.16 – 120 – K/W footprint only
3)
4.3.17 – 59 – K/W 300 mm
2
heatsink area
on PCB
3)
4.3.18 – 49 – K/W 600 mm
2
heatsink area
on PCB
3)