Datasheet

Data Sheet 10 Rev. 1.5, 2007-03-20
TLE 4268
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C
D
which can be calculated as follows:
C
D
= (∆t
rd
× I
D,c
)/∆V (1)
Definitions:
•
C
D
= delay capacitor
• ∆
t
rd
= delay time
•
I
D,c
= charge current, typical 12 µA
• ∆
V = V
DU
, typical 1.8 V
•
V
DU
= upper delay switching threshold at C
D
for reset delay time
The reset reaction time
t
rr
is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs
for delay capacitor of 47 nF. For other values for
C
D
the reaction time can be estimated
using the following equation:
t
rr
≈ 20 s/F × C
D
(2)
Figure 5 Timing (Watchdog disabled)
AED03010
Thermal
t
rd
Power-on-Reset Voltage Dip Secondary Overload
at OutputSpike
V
Ι
D,c
Ι
=
Vd
dt
V
Q
Q, rt
V
t
rr
<
rr
t
at Input
Undervoltage
Shutdown
C
D
t
V
RO
D
V
t
t
t
V
DU
V
DRL