Datasheet

Data Sheet 6 Rev. 2.51, 2012-01-20
TLE 4267
Figure 2 Pin Configuration (top view)
Table 3 Pin Definitions and Functions
Pin Symbol Function
1IInput; block to ground directly at the IC by a ceramic capacitor
2E2Inhibit; device is turned on by High signal on this pin; internal
pull-down resistor of 100 kΩ
7ROReset Output; open-collector output internally connected to
the output via a resistor of 30 kΩ
3, 4, 5, 10,
11, 12
GND Ground; connected to rear of chip
8DReset Delay; connect with capacitor to GND for setting delay
9E6Hold; see Table 1 for function; this input is connected to output
voltage via a pull-up resistor of 50 kΩ
13 Q 5-V Output; block to GND with 22-μF capacitor, ESR ≤ 3 Ω
6, 14 N.C. Not Connected
PG-DSO-14-30
AEP02710
E6
GND
N.C.
N.C.
RO
GND
Q
10
9
GND GND
1
2
3
4
5
GND
6
7D
14
13
12
11
E2
GND
8
Ι