Datasheet

TLE 4267
Data Sheet 3 Rev. 2.51, 2012-01-20
Application
The IC regulates an input voltage
V
I
in the range of 5.5 V < V
I
< 40 V to a nominal output
voltage of V
Q
= 5.0 V. A reset signal is generated for an output voltage of V
Q
< V
RT
(typ.
4.5 V). The reset delay can be set with an external capacitor. The device has two logic
inputs. A voltage of
V
E2
> 4.0 V given to the E2-pin (e.g. by ignition) turns the device on.
Depending on the voltage on pin E6 the IC may be hold in active-state even if V
E2
goes
to low level. This makes it simple to implement a self-holding circuit without external
components. When the device is turned off, the output voltage drops to 0 V and current
consumption tends towards 0 μA.
Design Notes for External Components
The input capacitor
C
I
is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1 Ω in series with
C
I
. The output capacitor is necessary for the stability of the
regulating circuit. Stability is guaranteed at values of ≥ 22 μF and an ESR of ≤ 3 Ω within
the operating temperature range.
Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturating of the power element.
The reset output RO is in high-state if the voltage on the delay capacitor
C
D
is greater or
equal
V
UD
. The delay capacitance C
D
is charged with the current I
D
for output voltages
greater than the reset threshold V
RT
. If the output voltage gets lower than V
RT
a fast
discharge of the delay capacitor C
D
sets in and as soon as V
CD
gets lower than V
LD
the
reset output RO is set to low-level (see Figure 6). The reset delay can be set within wide
range by dimensioning the capacitance of the external capacitor.