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5-V Low Drop Voltage Regulator TLE 4267 Features • • • • • • • • • • • • • • • • • Output voltage tolerance ≤ ±2% 400 mA output current capability Low-drop voltage Very low standby current consumption Input voltage up to 40 V Overvoltage protection up to 60 V (≤ 400 ms) Reset function down to 1 V output voltage ESD protection up to 2000 V Adjustable reset time On/off logic Overtemperature protection Reverse polarity protection Short-circuit proof Wide temperature range Suitable for use in automotive elec
TLE 4267 Application The IC regulates an input voltage VI in the range of 5.5 V < VI < 40 V to a nominal output voltage of VQ = 5.0 V. A reset signal is generated for an output voltage of VQ < VRT (typ. 4.5 V). The reset delay can be set with an external capacitor. The device has two logic inputs. A voltage of VE2 > 4.0 V given to the E2-pin (e.g. by ignition) turns the device on. Depending on the voltage on pin E6 the IC may be hold in active-state even if VE2 goes to low level.
TLE 4267 Table 1 Truth Table for Turn-ON/Turn-OFF Logic E2, Inhibit E6, Hold VQ Remarks L X OFF Initial state, Inhibit internally pulled-up H X ON Regulator switched on via Inhibit, by ignition for example H L ON Hold clamped active to ground by controller while Inhibit is still high X L ON Previous state remains, even ignition is shut off: self-holding state L L ON Ignition shut off while regulator is in self-holding state L H OFF Regulator shut down by releasing of Hold while
TLE 4267 PG-TO220-7-11 PG-TO263-7-1 PG-TO220-7-12 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 Ι RO D Q E2 GND E6 AEP01724 Ι RO D Q E2 GND E6 Ι RO D Q E2 GND E6 AEP01481 AEP02123 Figure 1 Pin Configuration (top view) Table 2 Pin Definitions and Functions Pin Symbol Function 1 I Input; block to ground directly at the IC by a ceramic capacitor 2 E2 Inhibit; device is turned on by High signal on this pin; internal pull-down resistor of 100 kΩ 3 RO Reset Output; open-collector output i
TLE 4267 PG-DSO-14-30 Ι E2 GND GND GND N.C. RO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 N.C.
TLE 4267 Saturation Control and Protection Circuit Temperature Sensor Input I Q 5V Output Control Amplifier Adjustment D Reset Delay Buffer Bandgap Reference Reset Generator RO Reset Output Turn-ON/Turn-OFF Logic E2 Inhibit Figure 3 Data Sheet E6 Hold GND Ground BLOCKDIAGRAM Block Diagram 7 Rev. 2.
TLE 4267 Table 4 Absolute Maximum Ratings TJ = -40 to 150 °C Parameter Symbol Limit Values Unit Notes Min. Max. VI VI II -42 42 V – – 60 V t ≤ 400 ms – – – internally limited VRO IRO -0.3 7 V – – – – internally limited VD ID -0.3 42 V – – – – – VQ IQ -0.3 7 V – – – – internally limited VE2 IE2 -42 42 V – -5 5 mA t ≤ 400 ms VE6 IE6 -0.3 7 V – – – mA internally limited IGND -0.
TLE 4267 Table 5 Operating Range Parameter Symbol Limit Values Unit Notes Min. Max. VI TJ 5.
TLE 4267 Table 6 Characteristics VI = 13.5 V; -40 °C < TJ < 125 °C; VE2 > 4 V (unless specified otherwise) Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Output voltage VQ 4.9 5 5.1 V 5 mA ≤ IQ ≤ 400 mA 6 V ≤ VI ≤ 26 V Output voltage VQ 4.9 5 5.1 V 5 mA ≤ IQ ≤ 150 mA 6 V ≤ VI ≤ 40 V Output current limiting IQ Iq 500 – – mA TJ = 25 °C – – 50 μA IC turned off Iq – 1.0 10 μA TJ = 25 °C Current consumption Iq = II - IQ Iq – 1.
TLE 4267 Table 6 Characteristics (cont’d) VI = 13.5 V; -40 °C < TJ < 125 °C; VE2 > 4 V (unless specified otherwise) Parameter Delay time Lower delay switching threshold Reset reaction time Symbol Limit Values Unit Test Condition Min. Typ. Max. tD VLD – 20 – ms Cd = 100 nF – 0.43 – V – tRR – 2 – μs Cd = 100 nF VU,INH VL,INH RINH ΔVINH IINH VU,HOLD VL,HOLD RHOLD – 3 4 V IC turned on 2 – – V IC turned off 50 100 200 kΩ – 0.2 0.5 0.
TLE 4267 ΙΙ Ι 1000 μF 470 nF Ι E2 VΙ Q 22 μF TLE 4267 RO Inhibit D Ιd VE2 ΙQ VC GND Ι GND 4.7 k Ω Ι RO VQ Hold VR VE6 CD AES01483 Figure 4 Test Circuit Input Inhibit; e.g. from Terminal 15 Reset to µC I e.g. 470nF E2 Q D TLE4267 100nF RO GND Data Sheet + 22µF E6 Hold from µC Figure 5 5V Output APPLICATIONDIAGRAM Application Circuit 12 Rev. 2.
TLE 4267 VΙ t VINH VU, INH VL, INH t < t RR VQ VRT VD VUD t t RR dV Ι D = dt C D VLD VD, SAT VRO t tD VRO, SAT t Power on Thermal Reset Shutdown Figure 6 Data Sheet Voltage Drop at Input Undervoltage at Output Secondary Load Spike Bounce Shutdown AET01985 Time Response 13 Rev. 2.
TLE 4267 VΙ t VE2 VU, INH 1) 5) VL, INH <1 μs VE6 VU, HOLD 2) VL, HOLD 4) t < 10 μs 6) 10) 7) t VQ VQ, NOM VRT 8) t VD VUD V LD VD, SAT VRO t RR tD 9) 3) VRO, SAT t t 1) 2) 3) 4) Enable active Hold inactive, pulled up by VQ Power-ON reset Hold active, clamped to GND by external μC 5) Enable inactive, clamped by int.
TLE 4267 Output Voltage VQ versus Temperature Tj AED01486 5.10 VQ Drop Voltage VDr versus Output Current IQ V AED01488 700 VDr V Ι = 13.5 V mV 5.00 500 400 T j = 125 C 4.90 300 T j = 25 C 200 4.80 100 4.70 -40 0 40 80 0 160 C 0 100 200 300 400 mA Charge Current ID versus Temperature Tj Delay Switching Threshold VUD versus Temperature Tj AED01485 22 AED01487 4.0 ΙD VUD μA V Ι = 13.5 V V 3.0 V Ι = 13.5 V 18 600 ΙQ Tj VUD VC = 0 V 2.5 16 ΙD 2.0 14 1.5 12 1.
TLE 4267 Current Consumption Iq versus Output Current IQ Current Consumption Iq versus Input Voltage VI AED01490 70 AED01491 15 Ιq Ιq mA R L = 25 Ω mA V Ι = 13.5 V 50 10 40 30 5 20 10 0 0 100 200 300 400 mA 0 600 0 20 10 30 ΙQ VΙ Output Current Limiting IQ versus Temperature Tj Output Current Limiting IQ versus Input Voltage VI AED01489 700 AED01987 700 mA Ι Q mA 600 500 500 ΙQ Tj = 25 C Tj = 125 C V Ι = 13.
TLE 4267 Output Voltage VQ versus Inhibit Voltage VINH AED01988 6 VQ Inhibit Current IINH versus Inhibit Voltage VINH AED01989 50 Ι INH μA V 5 40 4 30 3 20 2 10 1 0 0 1 2 3 4 0 5 V 6 VINH Data Sheet 17 0 1 2 3 4 5 V 6 V INH Rev. 2.
TLE 4267 Package Outlines 10 ±0.2 A 9.9 ±0.2 9.8 ±0.15 4.4 1.27 ±0.1 0.25 9.25 ±0.2 2.8 ±0.2 3.7 -0.15 3.7 ±0.3 C 0.5 ±0.1 2.4 7x 0.6 ±0.1 6x 1.27 1) 10.2 ±0.3 8.6 ±0.3 0...0.15 0.05 1.6 ±0.3 1) 13.4 17 ±0.3 15.65 ±0.3 8.5 1) 3.9 ±0.4 M A C 8.4 ±0.4 Typical All metal surfaces tin plated, except area of cut.
TLE 4267 4.4 10 ±0.2 1.27 ±0.1 0...0.3 B 0.05 2.4 0.1 4.7 ±0.5 2.7 ±0.3 7.551) 1±0.3 9.25 ±0.2 (15) A 8.5 1) 0...0.15 7 x 0.6 ±0.1 6 x 1.27 0.5 ±0.1 0.25 M A B 8˚ MAX. 1) Typical Metal surface min. X = 7.25, Y = 6.9 All metal surfaces tin plated, except area of cut. Figure 9 0.
TLE 4267 10 ±0.2 A 9.8 ±0.15 B 0...0.15 0.5 ±0.1 7x 0.6 ±0.1 1.27 9.25 ±0.2 0.05 13 ±0.5 11±0.5 C 1) 4.4 1.27 ±0.1 2.8 ±0.2 1) 13.4 17 ±0.3 15.65 ±0.3 8.5 1) 3.7 -0.15 2.4 0.25 M A B C Typical All metal surfaces tin plated, except area of cut.
TLE 4267 Figure 11 PG-DSO-14-30 (Plastic Dual Small Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
TLE 4267 Revision History Version Date Rev. 2.51 2012-02-20 Page 1: Coverpage added. Page 7: Figure 3 “Block Diagram” updated with clear label for reset output pin. Page 12: Figure 5 “Application Circuit” updated with clear labels for inhibit, hold, reset and reset delay pin. Rev. 2.
Edition 2012-01-20 Published by Infineon Technologies AG 81726 Munich, Germany © 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.
