Datasheet

Data Sheet 10 Rev. 2.8, 2007-03-20
TLE 4263
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C
D
which can be calculated as follows:
C
D
= (t
rd
× I
D,ch
)/∆V (1)
Definitions:
•
C
D
= delay capacitor
•
t
rd
= reset delay time
•
I
D,ch
= charge current, typical 60 µA
• ∆
V = V
DU
, typical 1.70 V
•
V
DU
= upper delay switching threshold at C
D
for reset delay time
Figure 5 Time Response, Watchdog with High-Frequency Clock
AET03066
I
V
V
Q
Q, rt
V
V
D
DU
V
V
DRL
RO
V
rd
t t
rr
<
rr
t
V d
t d
=
D, ch
I
D
C
Power-ON
Reset
Over-
temperature
at Input
Voltage Drop
Under-
voltage Spike
Secondary
Bounce
Load
t
t
t
t