Datasheet

C505/C505C/C505A/C505CA
Data Sheet 79 12.00
Figure 38
Lock Bit Access Timing
Figure 39
Version Byte Read Timing
H, L H, L
D0, D1 D0, D1
t
PCS
PMS
t
PMH
t
t
PCH
PWW
t
PMS
t
PRD
t
t
PDH
PDF
t
PMH
t
PRW
t
MCT03644
PMSEL1,0
Port 0
PROG
PRD
PALE should be low during a lock bit read / write cycle.Note:
e. g. FD
D0-7
t
PCS
PMS
t
t
PDH
PDF
t
PMH
t
MCT03645
Port 2
Port 0
PRD
PMSEL1,0
L, H
H
PRW
t
PRD
t
PCH
t
PROG must be high during a programming read cycle.Note: