Datasheet

C505/C505C/C505A/C505CA
Data Sheet 68 12.00
AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle)
(Operating Conditions apply)
(
C
L
for port 0, ALE and PSEN outputs = 100 pF; C
L
for all other outputs = 80 pF)
Program Memory Characteristics
*)
Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Parameter Symbol Limit Values Unit
16-MHz clock
Duty Cycle
0.4 to 0.6
Variable Clock
1/CLP= 2 MHz to 16 MHz
min. max. min. max.
ALE pulse width
t
LHLL
48 – CLP - 15 – ns
Address setup to ALE
t
AVLL
10 – TCL
Hmin
-15 – ns
Address hold after ALE
t
LLAX
10 – TCL
Hmin
-15 – ns
ALE to valid instruction in
t
LLIV
– 75 – 2 CLP - 50 ns
ALE to PSEN
t
LLPL
10 – TCL
Lmin
-15 – ns
PSEN
pulse width t
PLPH
73 – CLP+
TCL
Hmin
-15
– ns
PSEN
to valid instruction in t
PLIV
– 38 – CLP+
TCL
Hmin
- 50
ns
Input instruction hold after PSEN
t
PXIX
0 – 0 – ns
Input instruction float after PSEN
t
PXIZ
*)
– 15 – TCL
Lmin
-10 ns
Address valid after PSEN
t
PXAV
*)
20 – TCL
Lmin
- 5 – ns
Address to valid instruction in
t
AVIV
– 95 – 2 CLP +
TCL
Hmin
-55
ns
Address float to PSEN
t
AZPL
-5 – -5 – ns