Datasheet

C505/C505C/C505A/C505CA
Data Sheet 64 12.00
A/D Converter Characteristics of C505 and C505C
(Operating Conditions apply)
Notes see next page.
Clock calculation table :
Further timing conditions : t
ADC
min = 800 ns
t
IN
= 1 / f
OSC
= t
CLP
Parameter Symbol Limit Values Unit Test Condition
min. max.
Analog input voltage
V
AIN
V
AGND
-
0.2
V
AREF
+
0.2
V
1)
Sample time t
S
– 64 x t
IN
32 x t
IN
16 x t
IN
8 x t
IN
ns Prescaler ÷ 32
Prescaler
÷ 16
Prescaler
÷ 8
Prescaler
÷ 4
2)
Conversion cycle time t
ADCC
– 320 x t
IN
160 x t
IN
80 x t
IN
40 x t
IN
ns Prescaler ÷ 32
Prescaler
÷ 16
Prescaler
÷ 8
Prescaler
÷ 4
3)
Total unadjusted error T
UE
– ± 2LSBV
SS
+0.5V ≤ V
AIN
≤ V
DD
-0.5V
4)
Internal resistance of
reference voltage source
R
AREF
– t
ADC
/ 500
- 1
kΩ
t
ADC
in [ns]
5) 6)
Internal resistance of
analog source
R
ASRC
– t
S
/ 500
- 1
kΩ
t
S
in [ns]
2) 6)
ADC input capacitance C
AIN
– 50 pF
6)
Clock Prescaler
Ratio
ADCL1, 0 t
ADC
t
S
t
ADCC
÷ 32 1 1 32 x t
IN
64 x t
IN
320 x t
IN
÷ 16 1 0 16 x t
IN
32 x t
IN
160 x t
IN
÷ 8 0 1 8 x t
IN
16 x t
IN
80 x t
IN
÷ 4 0 0 4 x t
IN
8 x t
IN
40 x t
IN