Datasheet

C505/C505C/C505A/C505CA
Data Sheet 52 12.00
The following Table 11 contains the functional description of all C505A-4E/C505CA-4E pins which
are required for OTP memory programming.
Table 11
Pin Definitions and Functions in Programming Mode
Symbol
Pin Number
I/O
*)
Function
RESET 4 I Reset
This input must be at static “1“ (active) level during the whole
programming mode.
PMSEL0
PMSEL1
5
7
I
I
Programming mode selection pins
These pins are used to select the different access modes in
programming mode. PMSEL1,0 must satisfy a setup time to the
rising edge of PALE. When the logic level of PMSEL1,0 is
changed, PALE must be at low level.
PSEL
8IBasic programming mode select
This input is used for the basic programming mode selection
and must be switched according Figure 28.
PRD
9IProgramming mode read strobe
This input is used for read access control for OTP memory read,
Version Register read, and lock bit read operations.
PALE 10 I Programming address latch enable
PALE is used to latch the high address lines. The high address
lines must satisfy a setup and hold time to/from the falling edge
of PALE. PALE must be at low level when the logic level of
PMSEL1,0 is changed.
XTAL2 14 O XTAL2
Output of the inverting oscillator amplifier.
XTAL1 15 I XTAL1
Input to the oscillator amplifier.
V
SS
16 – Circuit ground potential
must be applied in programming mode.
V
DD
17 – Power supply terminal
must be applied in programming mode.
*) I = Input
O= Output
PMSEL1 PMSEL0 Access Mode
00Reserved
0 1 Read version bytes
1 0 Program/read lock bits
1 1 Program/read OTP memory byte