Datasheet

C505/C505C/C505A/C505CA
Data Sheet 40 12.00
10-Bit A/D Converter (C505A and C505CA only)
The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8
analog input channels. It operates with a successive approximation technique and uses self
calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D
converter provides the following features:
– 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors
The 10-bit ADC uses two clock signals for operation : the conversion clock f
ADC
(=1/t
ADC
) and the
input clock f
IN
(=1/t
IN
). f
ADC
is derived from the C505 system clock f
OSC
which is applied at the
XTAL pins. The input clock f
IN
is equal to f
OSC
The conversion f
ADC
clock is limited to a maximum
frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which
assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the
bits ADCL1 and ADCL0 of SFR ADCON1.
Figure 19
10-Bit A/D Converter Clock Selection
MCS03635
f
OSC
MUX
Clock Prescaler
Conversion Clock
Input Clock
f
ADC
IN
f
ADCL1
A / D
Converter
Condition:
ADC max
f
< 2 MHz
IN
f
=
f
OSC
=
CLP
1
32
8
4
16
ADCL0
MCU System Clock
Rate (f
OSC
)
f
IN
[MHz]
Prescaler
Ratio
f
ADC
[MHz]
ADCL1 ADCL0
2 MHz 2 ÷ 4 0.5 0 0
6 MHz 6 ÷ 4 1.5 0 0
8 MHz 8 ÷ 4200
12 MHz 12 ÷ 8 1.5 0 1
16 MHz 16 ÷ 8201
20 MHz 20 ÷ 16 1.25 1 0