Datasheet

C505/C505C/C505A/C505CA
Data Sheet 14 12.00
Reset and System Clock
The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pulldown resistor is internally connected to
V
SS
to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when
V
DD
is applied by connecting
the RESET pin to
V
DD
via a capacitor. Figure 6 shows the possible reset circuitries.
Figure 6
Reset Circuitries
RESET
+
a)
b)
c)
V
DD
+
V
DD
V
DD
C505
C505C
C505A
C505CA
RESET
C505
C505C
C505A
C505CA
&
RESET
C505
C505C
C505A
C505CA