Datasheet

C505/C505C/C505A/C505CA
Data Sheet 11 12.00
Figure 4
Block Diagram of the C505/C505C/C505A/C505CA
Port 0
8-bit digit. I/O
Port 2
8-bit digit. I/O
Port 3
8-bit digit. I/O
Port 0
Port 1
Port 2
Port 3
OSC & Timing
CPU
Timer 0
Timer 1
Timer 2
USART
XTAL1
XTAL2
RESET
ALE
PSEN
EA
Vss
V
DD
Oscillator Watchdog
A/D Converter
8-/10-Bit
1)
S&H
MUX
V
AGND
V
AREF
Port 1
8-bit digit. I/O /
8-bit analog In
16K or 32K
ROM/
256 Byte
XRAM
256 Byte
RAM
Emulation
Support
Logic
Programmable
Watchdog Timer
Full-CAN
Controller
256 Byte Reg./Dat
a
Interrupt Unit
8 datapointers
Port 4
2-bit digit. I/O
Port 4
C505C/C505CA only.
or 1K Byte
OTP
Byte
1)
1)
1) Please refer to Table 1 for device specific configuration.
Baudrate generator