Datasheet

C167CR
C167SR
Electrical Parameters
Data Sheet 74 V3.3, 2005-02
General Notes for the Following Timing Figures
These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.
1. The falling edge of signals RD
and WR/WRH/WRL/WrCS is controlled by the
Read/Write delay feature (bit BUSCON.RWDCx).
2. A bus cycle is extended here, if MCTC waitstates are selected or if the READY
input
is sampled inactive.
3. A bus cycle is extended here, if an MTTC waitstate is selected.