Datasheet

C167CR
C167SR
Electrical Parameters
Data Sheet 73 V3.3, 2005-02
Table 19 External Bus Cycle Timing (Operating Conditions apply)
Parameter Symbol Limits Unit
Min. Max.
Output delay from CLKOUT falling edge
Valid for: address, BHE
, early CS, write data out, ALE
tc
10
CC -2 11 ns
Output delay from CLKOUT rising edge
Valid for: latched CS
, ALE low
tc
11
CC -2 6 ns
Output delay from CLKOUT rising edge
Valid for: WR
low (no RW delay), RD low (no RW
delay)
tc
12
CC -2 8 ns
Output delay from CLKOUT falling edge
Valid for: RD
/WR low (with RW delay), RD high (with
RW delay)
tc
13
CC -2 6 ns
Input setup time to CLKOUT falling edge
Valid for: read data in
tc
14
SR 14 – ns
Input hold time after CLKOUT falling edge
Valid for: read data in
1)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD
. Therefore the read data may be removed immediately after the rising edge of RD. Address changes
before the end of RD
have also no impact on (demultiplexed) read cycles.
tc
15
SR 0 – ns
Output hold time after CLKOUT falling edge
Valid for: address, BHE
, early CS
2)
2) Due to comparable propagation delays (at comparable capacitive loads) the address does not change before
WR
goes high. The minimum output delay (tc
17min
) is therefore the actual value of tc
19
.
tc
17
CC -2 6 ns
Output hold time after CLKOUT edge
3)
Valid for: write data out
3) Not subject to production test - verified by design/characterization.
tc
18
CC -2 – ns
Output delay from CLKOUT falling edge
Valid for: WR
high
tc
19
CC -2 4 ns
Turn off delay after CLKOUT edge
3)
Valid for: write data out
tc
20
CC – 7 ns
Turn on delay after CLKOUT falling edge
3)
Valid for: write data out
tc
21
CC -5 – ns