Datasheet

C164CI/SI
C164CL/SL
Data Sheet 72 V2.0, 2001-05
AC Characteristics
Figure 24 CLKOUT Timing
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2)
The leading edge of the respective command depends on RW-delay.
3)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
4)
The next external bus cycle may start here.
CLKOUT
(Operating Conditions apply)
Parameter Symbol Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min. max. min. max.
CLKOUT cycle time
t
29
CC 40 40 2TCL 2TCL ns
CLKOUT high time
t
30
CC 14 – TCL - 6 – ns
CLKOUT low time
t
31
CC 10 – TCL - 10 – ns
CLKOUT rise time
t
32
CC – 4 – 4ns
CLKOUT fall time
t
33
CC – 4 – 4ns
CLKOUT rising edge to
ALE falling edge
t
34
CC 0 + t
A
10 + t
A
0 + t
A
10 + t
A
ns
CLKOUT
ALE
t
30
t
34
MUX/Tristate
3)
t
32
t
33
t
29
Running cycle
1)
t
31
Command
RD
, WR
2)
4)