Datasheet

C164CI/SI
C164CL/SL
Data Sheet 66 V2.0, 2001-05
Data valid to WR t
22
CC 20 + t
C
– 2TCL - 20
+
t
C
– ns
Data hold after WR
t
24
CC 10 + t
F
– TCL - 10
+
t
F
– ns
ALE rising edge after RD
,
WR
t
26
CC -10 + t
F
– -10 + t
F
– ns
Address hold after WR
2)
t
28
CC 0 + t
F
– 0 + t
F
– ns
ALE falling edge to CS
3)
t
38
CC -4 - t
A
10 - t
A
-4 - t
A
10 - t
A
ns
CS
low to Valid Data In
3)
t
39
SR – 40 +
t
C
+ 2t
A
– 3TCL - 20
+ t
C
+ 2t
A
ns
CS
hold after RD, WR
3)
t
41
CC 6 + t
F
– TCL - 14
+
t
F
– ns
ALE falling edge to RdCS
,
WrCS
(with RW-delay)
t
42
CC 16 + t
A
– TCL - 4
+
t
A
– ns
ALE falling edge to RdCS
,
WrCS
(no RW-delay)
t
43
CC -4 + t
A
– -4
+
t
A
– ns
RdCS
to Valid Data In
(with RW-delay)
t
46
SR – 16 + t
C
– 2TCL - 24
+ t
C
ns
RdCS
to Valid Data In
(no RW-delay)
t
47
SR – 36 + t
C
– 3TCL - 24
+
t
C
ns
RdCS
, WrCS Low Time
(with RW-delay)
t
48
CC 30 + t
C
– 2TCL - 10
+
t
C
– ns
RdCS
, WrCS Low Time
(no RW-delay)
t
49
CC 50 + t
C
– 3TCL - 10
+
t
C
– ns
Data valid to WrCS
t
50
CC 26 + t
C
– 2TCL - 14
+ t
C
– ns
Data hold after RdCS
t
51
SR 0 – 0 – ns
Data float after RdCS
(with RW-delay)
1)
t
53
SR – 20 + t
F
– 2TCL - 20
+
2t
A
+ t
F
1)
ns
Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A
+ t
C
+ t
F
(80 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min. max. min. max.