Datasheet

C164CI/SI
C164CL/SL
Data Sheet 63 V2.0, 2001-05
Figure 18 External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
Data OutAddress
Address Data In
t
38
Address
ALE
CSxL
A21-A16
(A15-A8)
BHE
, CSxE
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL
,
WRH
WrCSx
t
5
t
16
t
17
t
6
t
7
t
39
t
40
t
25
t
27
t
18
t
19
t
15
t
47
t
13
t
49
t
22
t
23
t
13
t
49
t
9
t
43
t
43
t
9
t
11
t
45
t
11
t
45
t
50
t
51
t
54
t
52
t
56