Datasheet

C164CI/SI
C164CL/SL
Data Sheet 61 V2.0, 2001-05
Figure 16 External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Normal ALE
A21-A16
(A15-A8)
BHE
, CSxE
Data In
Data OutAddress
Address
t
38
t
44
t
10
Address
ALE
CSxL
BUS
Read Cycle
RD
RdCSx
BUS
Write Cycle
WR,
WRL
,
WRH
WrCSx
t
5
t
16
t
17
t
6
t
7
t
39
t
40
t
25
t
27
t
18
t
19
t
14
t
46
t
12
t
48
t
10
t
22
t
23
t
44
t
12
t
48
t
8
t
42
t
42
t
8
t
50
t
51
t
54
t
52
t
56