Datasheet

C164CI/SI
C164CL/SL
Data Sheet 51 V2.0, 2001-05
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register
RSTCON under software control.
Table 11 associates the combinations of these three bits with the respective clock
generation mode.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001
B
) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
f
CPU
is half the frequency of f
OSC
and the high and low time of f
CPU
(i.e.
the duration of an individual TCL) is defined by the period of the input clock
f
OSC
.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of f
OSC
for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see Table 11). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
f
CPU
= f
OSC
× F). With every F’th transition of f
OSC
the PLL circuit synchronizes the CPU
clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock
frequency does not change abruptly.
Table 11 C164CI Clock Generation Modes
CLKCFG
1)
(RP0H.7-5)
1)
Please note that pin P0.15 (corresponding to RP0H.7) is inverted in emulation mode, and thus also in EHM.
CPU Frequency
f
CPU
= f
OSC
× F
External Clock
Input Range
2)
2)
The external clock input range refers to a CPU clock range of 10 … 25 MHz.
Notes
11 1
f
OSC
× 4 2.5 to 6.25 MHz Default configuration
110
f
OSC
× 3 3.33 to 8.33 MHz –
101
f
OSC
× 2 5 to 12.5 MHz –
100
f
OSC
× 5 2 to 5 MHz –
011
f
OSC
× 1 1 to 25 MHz Direct drive
3)
3)
The maximum frequency depends on the duty cycle of the external clock signal.
010 f
OSC
× 1.5 6.66 to 16.66 MHz –
001
f
OSC
/ 2 2 to 50 MHz CPU clock via prescaler
000
f
OSC
× 2.5 4 to 10 MHz –