Datasheet

C164CI/SI
C164CL/SL
Data Sheet 50 V2.0, 2001-05
AC Characteristics
Definition of Internal Timing
The internal operation of the C164CI is controlled by the internal CPU clock
f
CPU
. Both
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).
Figure 11 Generation Mechanisms for the CPU Clock
The CPU clock signal
f
CPU
can be generated from the oscillator clock signal f
OSC
via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
f
CPU
. This influence must
be regarded when calculating the timings for the C164CI.
Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4.
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
MCT04338
f
OSC
f
CPU
Phase Locked Loop Operation
TCL
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
TCL
TCL
TCL
TCL
TCL