D at a S he e t, V 2. 0 , M ay 20 0 1 C 1 6 4C I/ SI C 1 6 4C L/ SL 16 -B it S in gl e -C hi p Mi cro c on tro ll e r Mi cro c on tr ol le rs N e v e r s t o p t h i n k i n g .
Edition 2001-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved.
D at a S he e t, V 2. 0 , M ay 20 0 1 C 1 6 4C I/ SI C 1 6 4C L/ SL 16 -B it S in gl e -C hi p Mi cro c on tro ll e r Mi cro c on tr ol le rs N e v e r s t o p t h i n k i n g .
C164CI Revision History: 2001-05 Previous Version: 1999-08 1998-02 04.97 V2.0 (Preliminary) (Advance Information) Page Subjects (major changes since last revision)1) All Converted to Infineon layout 1 Operating frequency up to 25 MHz 1 et al.
16-Bit Single-Chip Microcontroller C166 Family C164CI C164CI/SI, C164CL/SL • High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Total Linear Address Space for Code an
C164CI/SI C164CL/SL • Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards • On-Chip Bootstrap Loader • 80-Pin MQFP Package, 0.65 mm pitch This document describes several derivatives of the C164 group. Table 1 enumerates these derivatives and summarizes the differences.
C164CI/SI C164CL/SL Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • the derivative itself, i.e. its function set, the temperature range, and the supply voltage • the package and the type of delivery. For the available ordering codes for the C164CI please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.
C164CI/SI C164CL/SL VDD P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 P8.3/CC19IO/* P8.2/CC18IO/* P8.1/CC17IO/* P8.0/CC16IO/* NMI RSTOUT RSTIN P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11/EXIN/T7IN P1H.2/A10/CC6POS2/EX2IN P1H.1/A9/CC6POS1/EX1IN 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VAGND Pin Configuration (top view) C164CI VDD VSS 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS P1H.0/A8/CC6POS0/EX0IN P1L.7/A7/CTRAP P1L.
C164CI/SI C164CL/SL Table 2 Pin Definitions and Functions Symbol Pin No. Input Outp. Function P5 I Port 5 is an 8-bit input-only port with Schmitt-Trigger charact. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp. AN5, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
C164CI/SI C164CL/SL Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Outp. Function P4 IO Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 4 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special).
C164CI/SI C164CL/SL Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Outp. Function EA/VPP 28 I External Access Enable pin. A low level at this pin during and after Reset forces the C164CI to latch the configuration from PORT0 and pin RD, and to begin instruction execution out of external memory. A high level forces the C164CI to latch the configuration from pins RD and ALE, and to begin instruction execution out of the internal program memory.
C164CI/SI C164CL/SL Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Outp. PORT1 IO P1L.0-7 47-52, 57-59 P1H.0-7 59, 62-68 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 47 48 49 50 51 52 57 58 I/O O I/O O I/O O O I P1H.0 59 P1H.1 62 P1H.2 63 P1H.3 64 I I I I I I I P1H.4 P1H.5 P1H.6 P1H.7 65 66 67 68 I/O I/O I/O I/O Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits.
C164CI/SI C164CL/SL Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Outp. Function XTAL2 XTAL1 54 55 O I XTAL2: XTAL1: RSTIN 69 I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C164CI. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter.
C164CI/SI C164CL/SL Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Outp. Function P8 IO I/O I I/O O I/O I I/O O Port 8 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special).
C164CI/SI C164CL/SL Functional Description The architecture of the C164CI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C164CI.
C164CI/SI C164CL/SL Memory Organization The memory space of the C164CI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.
C164CI/SI C164CL/SL External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
C164CI/SI C164CL/SL Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C164CI’s instructions can be executed in just one machine cycle which requires 2 CPU clocks (4 TCL).
C164CI/SI C164CL/SL The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.
C164CI/SI C164CL/SL Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C164CI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C164CI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.
C164CI/SI C164CL/SL Table 3 C164CI Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number Fast External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H 18H Fast External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H 19H Fast External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H 1AH Fast External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH 1BH GPT1 Timer 2 T2IR T2IE T2INT 00’0088H 22H GPT1 Timer 3 T3IR T3IE T3INT 0
C164CI/SI C164CL/SL Table 3 C164CI Interrupt Nodes (cont’d) Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM 6 Timer 12 T12IR T12IE T12INT 00’0134H 4DH CAPCOM 6 Timer 13 T13IR T13IE T13INT 00’0138H 4EH CC6EIE CC6EINT 00’013CH 4FH CAPCOM 6 Emergency CC6EIR Data Sheet 18 V2.
C164CI/SI C164CL/SL The C164CI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
C164CI/SI C164CL/SL The Capture/Compare Unit CAPCOM2 The general purpose CAPCOM2 unit supports generation and control of timing sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.
C164CI/SI C164CL/SL The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions. The compare channel can generate a single PWM output signal and is further used to modulate the capture/ compare output signals.
C164CI/SI C164CL/SL General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates three 16-bit timers. Each timer may operate independently in a number of different modes, or may be concatenated with another timer.
C164CI/SI C164CL/SL U/D T2EUD fCPU 2n : 1 T2IN Interrupt Request (T2IR) GPT1 Timer T2 T2 Mode Control Reload Capture fCPU Interrupt Request (T3IR) 2n : 1 Toggle FF T3 Mode Control T3IN GPT1 Timer T3 T3OTL U/D T3EUD Other Timers Capture Reload T4IN fCPU 2n : 1 T4 Mode Control GPT1 Timer T4 Interrupt Request (T4IR) U/D T4EUD Mct04825_4.vsd n = 3 … 10 Figure 6 Data Sheet Block Diagram of GPT1 23 V2.
C164CI/SI C164CL/SL Real Time Clock The Real Time Clock (RTC) module of the C164CI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32) and is therefore independent from the selected clock generation mode of the C164CI. All timers count up.
C164CI/SI C164CL/SL A/D Converter For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry.
C164CI/SI C164CL/SL Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
C164CI/SI C164CL/SL CAN-Module The integrated CAN-Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides Full CAN functionality on up to 15 message objects. Message object 15 may be configured for Basic CAN functionality.
C164CI/SI C164CL/SL Parallel Ports The C164CI provides up to 59 I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs.
C164CI/SI C164CL/SL Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and supplies the CPU with the PLL clock signal.
C164CI/SI C164CL/SL Power Management The C164CI provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the C164CI into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may optionally continue running).
C164CI/SI C164CL/SL Instruction Set Summary Table 6 lists the instructions of the C164CI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailled description of each instruction.
C164CI/SI C164CL/SL Table 6 Instruction Set Summary (cont’d) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Data Sheet Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand with zero extension Jump absolute/indirect/relative if condition is met Bytes 2/4 2/4 2/4 4 Jump absolute t
C164CI/SI C164CL/SL Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C164CI in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name.
C164CI/SI C164CL/SL Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr. Reset Value C1MCFGn EFn6H X --- CAN Message Configuration Register (msg. n) C1MCRn EFn0H X --- CAN Message Control Register (msg. n) UUUUH C1PCIR EF02H X --- CAN1 Port Control / Interrupt Register C1UARn EFn2H X --- CAN Upper Arbitration Register (msg.
C164CI/SI C164CL/SL Table 7 Name CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC C164CI Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. b F174H E BAH FE76H 3BH b F176H Reset Value CAPCOM Reg. 26 Interrupt Ctrl. Reg. 0000H CAPCOM Register 27 0000H E BBH 3CH CAPCOM Reg. 27 Interrupt Ctrl. Reg. 0000H CAPCOM Register 28 0000H E BCH FE7AH 3DH b F184H E C2H CAPCOM Reg. 28 Interrupt Ctrl. Reg. 0000H CAPCOM Register 29 0000H CAPCOM Reg.
C164CI/SI C164CL/SL Table 7 Name C164CI Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. Reset Value 1010H CTCON b FF30H 98H CAPCOM 6 Compare Timer Ctrl. Reg.
C164CI/SI C164CL/SL Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr. OPDAT EDC4H X --- Reset Value OTP Progr. Interface Data Register 0000H P0H b FF02H 81H Port 0 High Reg. (Upper half of PORT0) 00H P0L b FF00H 80H Port 0 Low Reg. (Lower half of PORT0) 00H P1H b FF06H 83H Port 1 High Reg. (Upper half of PORT1) 00H P1L b FF04H 82H Port 1 Low Reg.
C164CI/SI C164CL/SL Table 7 C164CI Registers, Ordered by Name (cont’d) Name Physical Address RTCH F0D6H E 6BH RTC High Register no RTCL F0D4H E 6AH RTC Low Register no S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0H D8H Serial Channel 0 Control Register 0000H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Ctrl. Reg. 0000H FEB2H 59H Serial Channel 0 Receive Buffer Reg.
C164CI/SI C164CL/SL Table 7 Name T12IC C164CI Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. Reset Value b F190H E C8H CAPCOM 6 Timer 12 Interrupt Ctrl. Reg. 0000H T12OF F034H E 1AH CAPCOM 6 Timer 12 Offset Register 0000H T12P F030H E 18H E CCH CAPCOM 6 Timer 12 Period Register 0000H CAPCOM 6 Timer 13 Interrupt Ctrl. Reg.
C164CI/SI C164CL/SL Table 7 Name C164CI Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. XP3IC b F19EH E CFH ZEROS b FF1CH 8EH Reset Value PLL/RTC Interrupt Control Register 0000H Constant Value 0’s Register (read only) 0000H 1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source. Note: The three registers of the OTP programming interface are, of course, only implemented in the OTP versions of the C164CI.
C164CI/SI C164CL/SL Absolute Maximum Ratings Table 8 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. TST TJ VDD -65 150 °C – -40 150 °C under bias -0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 VDD + 0.5 V – Input current on any pin during overload condition – -10 10 mA – Absolute sum of all input currents during overload condition – – |100| mA – Power dissipation PDISS – 1.
C164CI/SI C164CL/SL Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C164CI. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 9 Operating Condition Parameters Parameter Symbol Limit Values min. Digital supply voltage VDD VSS IOV Overload current Absolute sum of overload Σ|IOV| Unit Notes max. 4.75 5.5 V Active mode, fCPUmax = 25 MHz 2.51) 5.
C164CI/SI C164CL/SL Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C164CI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C164CI will provide signals with the respective characteristics.
C164CI/SI C164CL/SL DC Characteristics (cont’d) (Operating Conditions apply)1) Parameter Symbol Limit Values min. Input leakage current (all other) RSTIN inactive current 6) 6) RSTIN active current RD/WR inact.
C164CI/SI C164CL/SL Table 10 Current Limits for Port Output Drivers Port Output Driver Mode Maximum Output Current (IOLmax, -IOHmax)1) Nominal Output Current (IOLnom, -IOHnom)2) Strong driver 10 mA 2.5 mA Medium driver 4.0 mA 1.0 mA Weak driver 0.5 mA 0.1 mA 1) An output current above |IOXnom | may be drawn from up to three pins at the same time. For any group of 16 neighboring port output pins the total output current in each direction (Σ IOL and Σ -IOH) must remain below 50 mA.
C164CI/SI C164CL/SL Power Consumption C164CI (OTP) (Operating Conditions apply) Parameter Symbol min. max. Power supply current (active) with all peripherals active IDD – 10 + 3.5 × fCPU mA RSTIN = VIL fCPU in [MHz]1) Idle mode supply current with all peripherals active IIDX – 5+ mA 1.
C164CI/SI C164CL/SL Ι µA 1500 1250 I IDOmax 1000 I IDOtyp 750 500 I PDRmax 250 I PDOmax 0 0 4 8 12 16 MHz f OSC MCD04433 Figure 8 Data Sheet Idle and Power Down Supply Current as a Function of Oscillator Frequency 47 V2.
C164CI/SI C164CL/SL I [mA] 100 80 IDD5max IDD5typ 60 40 IIDX5max IIDX5typ 20 10 Figure 9 Data Sheet 15 20 25 fCPU [MHz] Supply/Idle Current as a Function of Operating Frequency for ROM Derivatives 48 V2.
C164CI/SI C164CL/SL I [mA] IDD5max 100 IDD5typ 80 60 IIDX5max 40 IIDX5typ 20 10 Figure 10 Data Sheet 15 20 25 fCPU [MHz] Supply/Idle Current as a Function of Operating Frequency for OTP Derivatives 49 V2.
C164CI/SI C164CL/SL AC Characteristics Definition of Internal Timing The internal operation of the C164CI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).
C164CI/SI C164CL/SL P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Table 11 C164CI Clock Generation Modes CLKCFG1) CPU Frequency (RP0H.7-5) fCPU = fOSC × F fOSC × 4 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 fOSC × 3 fOSC × 2 fOSC × 5 fOSC × 1 fOSC × 1.5 fOSC / 2 fOSC × 2.5 External Clock Input Range2) Notes 2.5 to 6.
C164CI/SI C164CL/SL Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL.
C164CI/SI C164CL/SL Direct Drive When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC.
C164CI/SI C164CL/SL AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 12 External Clock Drive Characteristics Parameter Symbol min. Oscillator period High time2) Low time 2) Rise time 2) 2) Fall time tOSC t1 t2 t3 t4 Prescaler 2:1 Direct Drive 1:1 PLL 1:N Unit max. min. max. min. max.
C164CI/SI C164CL/SL A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Symbol VAREF SR VAGNDSR VAIN SR fBC tC CC Limit Values Unit Test Conditions min. max. 4.0 VSS - 0.1 VAGND VDD + 0.1 V VSS + 0.2 V VAREF V 0.5 6.
C164CI/SI C164CL/SL 8) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from Table 14.
C164CI/SI C164CL/SL Testing Waveforms 2.4 V 1.8 V 1.8 V Test Points 0.8 V 0.8 V 0.45 V AC inputs during testing are driven at 2.4 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIH min for a logic ’1’ and VIL max for a logic ’0’. MCA04414 Figure 14 Input Output Waveforms VLoad + 0.1 V VOH - 0.1 V Timing Reference Points VLoad - 0.1 V VOL + 0.
C164CI/SI C164CL/SL Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed.
C164CI/SI C164CL/SL Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
C164CI/SI C164CL/SL Multiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max. – -4 + tA – ns Address float after RdCS, t44 CC – WrCS (with RW delay) 0 – 0 ns Address float after RdCS, t45 CC – WrCS (no RW delay) 20 – TCL ns ALE fall.
C164CI/SI C164CL/SL t5 t16 t25 ALE t38 t39 t40 CSxL t17 A21-A16 (A15-A8) BHE, CSxE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t8 Data In t10 t14 RD t42 t44 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address t8 WR, WRL, WRH t42 Data Out t56 t10 t22 t12 t50 t44 WrCSx t48 Figure 16 Data Sheet External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE 61 V2.
C164CI/SI C164CL/SL t5 t16 t25 t39 t40 t17 t27 ALE t38 CSxL A21-A16 (A15-A8) BHE, CSxE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t10 t8 t14 RD t4 t42 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address Data Out t10 t8 WR, WRL, WRH t44 t42 t56 t22 t12 t50 WrCSx t48 Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet 62 V2.
C164CI/SI C164CL/SL t5 t16 t25 ALE t38 t39 t40 CSxL t17 A21-A16 (A15-A8) BHE, CSxE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t9 Data In t11 t15 RD t43 t13 t45 t47 RdCSx t51 t52 t49 Write Cycle BUS t23 Address t9 WR, WRL, WRH t43 Data Out t56 t11 t22 t45 t13 t50 WrCSx t49 Figure 18 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE 63 V2.
C164CI/SI C164CL/SL t5 t16 t25 t39 t40 t17 t27 ALE t38 CSxL A21-A16 (A15-A8) BHE, CSxE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t9 t11 RD t15 t13 t43 t45 RdCSx t51 t52 t47 t49 Write Cycle BUS t23 Address Data Out t56 t9 WR, WRL, WRH t43 t11 t22 t45 t13 t50 WrCSx t49 Figure 19 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet 64 V2.
C164CI/SI C164CL/SL AC Characteristics Demultiplexed Bus (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
C164CI/SI C164CL/SL Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
C164CI/SI C164CL/SL Demultiplexed Bus (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. max. min. max.
C164CI/SI C164CL/SL t5 t16 t26 ALE t38 t39 t41 CSxL t17 A21-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t20 t18 Read Cycle BUS (D15-D8) D7-D0 Data In t8 t14 RD t12 t42 RdCSx t51 t53 t46 t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t22 t12 t50 t42 WrCSx t48 Figure 20 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE 68 V2.
C164CI/SI C164CL/SL t5 t16 t26 ALE t38 t39 t41 CSxL t17 A21-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t20 t18 Read Cycle BUS (D15-D8) D7-D0 Data In t8 t14 RD t12 t42 t51 t53 t46 RdCSx t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t22 t12 t50 t42 WrCSx t48 Figure 21 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE 69 V2.
C164CI/SI C164CL/SL t5 t16 t26 ALE t38 t39 t41 CSxL t17 A21-A16 A15-A0 BHE, CSxE t28 Address t6 Read Cycle BUS (D15-D8) D7-D0 t55 t21 t18 Data In t9 t15 RD t43 t13 t47 RdCSx t51 t68 t49 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t57 t9 t22 WR, WRL,WRH t13 t50 t43 WrCSx t49 Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet 70 V2.
C164CI/SI C164CL/SL t5 t16 t26 ALE t38 t39 t41 CSxL t17 A21-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t21 t18 Read Cycle BUS (D15-D8) D7-D0 Data In t9 t15 RD t13 t43 t51 t68 t47 RdCSx t49 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t57 t9 t22 WR, WRL, WRH t13 t50 t43 WrCSx t49 Figure 23 Data Sheet External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE 71 V2.
C164CI/SI C164CL/SL AC Characteristics CLKOUT (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge t29 t30 t31 t32 t33 t34 max. min. max.
C164CI/SI C164CL/SL External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C164CI can be accessed (during hold states) by an external master like an asynchronous SRAM. Table 16 XRAM Access Timing (Operating Conditions apply) Parameter Symbol Limit Values min.
C164CI/SI C164CL/SL Package Outlines GPM05249 P-MQFP-80-7 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 74 Dimensions in mm V2.
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