Datasheet

XC167CI-16F
Derivatives
Electrical Parameters
Data Sheet 81 V1.3, 2006-08
Figure 23 READY Timing
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
a READY-controlled waitstate is inserted (
tp
RDY
),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see
tp
E
) before the READY input is
evaluated.
MCT05559
READY
Asynchron.
Not Rdy
READY
Data Out
tc
25
tc
30
D15-D0
(write)
READY
Synchronous
Not Rdy
READY
Data In
D15-D0
(read)
tc
10
RD, WR
tp
D
tp
E
tp
RDY
tp
F
CLKOUT
tc
20
tc
30
tc
31
tc
31
tc
30
tc
31
tc
30
tc
31
tc
30
tc
31