Datasheet

XC167CI-16F
Derivatives
Electrical Parameters
Data Sheet 70 V1.3, 2006-08
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
f
MC
. Therefore,
the number of VCO cycles can be represented as K × N, where N is the number of
consecutive
f
MC
cycles (TCM).
For a period of N × TCM the accumulated PLL jitter is defined by the deviation D
N
:
D
N
[ns] = ±(1.5 + 6.32 × N / f
MC
); f
MC
in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D
3
= ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K × N < 95. For longer periods the K × N = 95 value can be
used. This steady value can be approximated by: D
Nmax
[ns] = ±(1.5 + 600 / (K × f
MC
)).
Figure 16 Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
Different frequency bands can be selected for the VCO, so the operation of the PLL can
be adjusted to a wide range of input and output frequencies:
MCD05566
N
0
±1
±2
±3
±4
±5
±6
±7
±8
Acc. jitter D
N
051015 20 25
ns
K = 15
K = 12
K = 10
K = 8
K = 6 K = 5
1
10 MHz
20 MHz
40 MHz