Datasheet

XC167CI-16F
Derivatives
Electrical Parameters
Data Sheet 68 V1.3, 2006-08
4.4 AC Parameters
4.4.1 Definition of Internal Timing
The internal operation of the XC167 is controlled by the internal master clock f
MC
.
The master clock signal
f
MC
can be generated from the oscillator clock signal f
OSC
via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
f
MC
.
This influence must be regarded when calculating the timings for the XC167.
Figure 15 Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 15 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
f
CPU
. The CPU clock can have the
same frequency as the master clock (
f
CPU
= f
MC
) or can be the master clock divided by
two:
f
CPU
= f
MC
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
MCT05555
Phase Locked Loop Operation (1:N)
f
OSC
Direct Clock Drive (1:1)
Prescaler Operation (N:1)
f
MC
f
OSC
f
MC
f
OSC
f
MC
TCM
TCM
TCM