Datasheet

XC167CI-16F
Derivatives
Electrical Parameters
Data Sheet 67 V1.3, 2006-08
Sample time and conversion time of the XC167’s A/D Converter are programmable. In
compatibility mode, the above timing can be calculated using Table 15.
The limit values for
f
BC
must not be exceeded when selecting ADCTC.
Converter Timing Example:
Table 15 A/D Converter Computation Table
1)
1) These selections are available in compatibility mode. An improved mechanism to control the ADC input clock
can be selected.
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock
f
BC
ADCON.13|12
(ADSTC)
Sample Time
t
S
00 f
SYS
/ 4 00 t
BC
× 8
01
f
SYS
/ 2 01 t
BC
× 16
10
f
SYS
/ 16 10 t
BC
× 32
11
f
SYS
/ 8 11 t
BC
× 64
Assumptions:
f
SYS
= 40 MHz (i.e. t
SYS
= 25 ns), ADCTC = ‘01’, ADSTC = ‘00’
Basic clock
f
BC
= f
SYS
/ 2 = 20 MHz, i.e. t
BC
= 50 ns
Sample time
t
S
= t
BC
× 8 = 400 ns
Conversion 10-bit:
With post-calibr.
t
C10P
= 52 × t
BC
+ t
S
+ 6 × t
SYS
= (2600 + 400 + 150) ns = 3.15 µs
Post-calibr. off
t
C10
= 40 × t
BC
+ t
S
+ 6 × t
SYS
= (2000 + 400 + 150) ns = 2.55 µs
Conversion 8-bit:
With post-calibr.
t
C8P
= 44 × t
BC
+ t
S
+ 6 × t
SYS
= (2200 + 400 + 150) ns = 2.75 µs
Post-calibr. off
t
C8
= 32 × t
BC
+ t
S
+ 6 × t
SYS
= (1600 + 400 + 150) ns = 2.15 µs