Datasheet

XC167CI-16F
Derivatives
Functional Description
Data Sheet 39 V1.3, 2006-08
Figure 7 Block Diagram of GPT1
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
MCA05563
Aux. Timer T2
2
n
:1
T2
Mode
Control
Capture
U/D
Basic Clock
f
GPT
T3CON.BPS1
T3OTL
T3OUT
Toggle
Latch
T2IN
T2EUD
Reload
Core Timer T3
T3
Mode
Control
T3IN
T3EUD
U/D
Interrupt
Request
(T3IRQ)
T4
Mode
Control
U/D
Aux. Timer T4
T4EUD
T4IN
Reload
Capture
Interrupt
Request
(T4IRQ)
Interrupt
Request
(T2IRQ)