Datasheet

XC167CI-16F
Derivatives
Functional Description
Data Sheet 21 V1.3, 2006-08
3 Functional Description
The architecture of the XC167 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC167.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC167.
Figure 3 Block Diagram
Interrupt Bus
XTAL
MCB04323_x7.vsd
Osc / PLL
Clock Generation
RTC WDT
GPT
T2
T3
T4
T5
T6
SSC0
BRGen
(SPI)
ASC1
BRGen
(USART)
ADC
8/10-Bit
16
Channels
CC2
T7
T8
EBC
XBUS Control
External Bus
Control
ProgMem
Flash
128 KBytes
P 20
4
16
Port 5
16
PSRAM DPRAM DSRAM
C166SV2-Core
PMU
DMU
CPU
ASC0
BRGen
(USART)
IIC
BRGen
SSC1
BRGen
(SPI)
CC1
T0
T1
Twin
CAN
A B
PORT1 PORT0Port 2Port 3Port 4Port 6P 7Port 9
16
81588
66
Interrupt & PEC
Peripheral Data Bus
OCDS
Debug Support
CC6
T12
T13