Data Sheet, V1.3, Aug.
Edition 2006-08 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2006. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”).
Data Sheet, V1.3, Aug.
XC167CI-16F Derivatives XC167 Revision History: V1.3, 2006-08 Previous Version(s): V1.2, 2006-03 V1.1, 2003-06 V1.0, 2002-10 Page Subjects (major changes since last revision) 13 Description of the TRST signal modified. 19 Footnote added about pins XTAL1/XTAL3 belonging to VDDI power domain. 53 Instructions Set Summary improved. 60 Footnote added about amplitude at XTAL1 pin. 85 Green package added.
XC167CI-16F Derivatives Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 3.1 3.2 3.3 3.4 3.
16-Bit Single-Chip Microcontroller with C166SV2 Core XC166 Family 1 • • • • • • • • XC167 Summary of Features High Performance 16-bit CPU with 5-Stage Pipeline – 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution) – 1-Cycle Multiplication (16 ×16 bit), Background Division (32 / 16 bit) in 21 Cycles – 1-Cycle Multiply-and-Accumulate (MAC) Instructions – Enhanced Boolean Bit Manipulation Facilities – Zero-Cycle Jump Execution – Additional Instructions to Support HLL and Operating S
XC167CI-16F Derivatives Summary of Features • • • • • • Up to 12 Mbytes External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses – Selectable Address Bus Width – 16-Bit or 8-Bit Data Bus Width – Five Programmable Chip-Select Signals – Hold- and Hold-Acknowledge Bus Arbitration Support Up to 103 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis On-Chip Bootstr
XC167CI-16F Derivatives Summary of Features Table 1 XC167 Derivative Synopsis Derivative1) Temp.
XC167CI-16F Derivatives General Device Information 2 General Device Information 2.1 Introduction The XC167 derivatives are high-performance members of the Infineon XC166 Family of full featured single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 40 million instructions per second) with high peripheral functionality and enhanced IO-capabilities.
XC167CI-16F Derivatives General Device Information 2.2 Pin Configuration and Definition P1L.7/A7/CTRAP/CC22IO P1L.6/A6/COUT63 P1L.5/A5/COUT62 P1L.4/A4/CC62 P1L.3/A3/COUT61 P1L.2/A2/CC61 P1L.1/A1/COUT60 P1L.0/A0/CC60 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 N.C. N.C. VSSP VDDP P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11/SCLK1/E*) P1H.2/A10/CC6POS2/MTSR1 P1H.1/A9/CC6POS1/MRST1 P1H.
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions Pin Num. Input Outp. Function P20.12 3 IO For details, please refer to the description of P20. NMI I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC167 into power down mode.
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. P7 P7.4 15 P7.5 16 P7.6 17 P7.7 18 Data Sheet Input Outp. Function IO Port 7 is a 4-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 7 is selectable (standard or special).
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. P9 P9.0 21 P9.1 22 P9.2 23 P9.3 24 P9.4 25 P9.5 26 Data Sheet Input Outp. Function IO Port 9 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 9 is selectable (standard or special).
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. P5 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.10 P5.11 P5.8 P5.9 P5.6 P5.7 P5.12 P5.13 P5.14 P5.15 29 30 31 32 33 34 35 36 37 38 39 40 43 44 45 46 Data Sheet Input Outp. Function I Port 5 is a 16-bit input-only port. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN10, T6EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. P2 P2.8 49 P2.9 50 P2.10 51 P2.11 52 P2.12 53 P2.13 54 P2.14 55 P2.15 56 TRST 57 Data Sheet Input Outp. Function IO Port 2 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 2 is selectable (standard or special).
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. P3 Input Outp. Function IO I O I O I/O I I O I I I I I/O I/O O I I/O I O O I I/O I O O Port 3 is a 15-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 3 is selectable (standard or special).
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. P4 P4.0 P4.1 P4.2 P4.3 P4.4 80 81 82 83 84 P4.5 85 P4.6 86 P4.7 87 Data Sheet Input Outp. Function IO Port 4 is an 8-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output (configurable as push/pull or open drain driver). The input threshold of Port 4 is selectable (standard or special).
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. P20 Input Outp. Function IO Port 20 is a 6-bit bidirectional I/O port. Each pin can be programmed for input (output driver in high-impedance state) or output. The input threshold of Port 20 is selectable (standard or special). The following Port 20 pins also serve for alternate functions: External Memory Read Strobe, activated for RD every external instruction or data read access.
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. PORT0 P0L.0 P0L.7, P0H.0, P0H.1, P0H.2 P0H.7 95 102, 105, 106, 111 116 Input Outp. Function IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. Each pin can be programmed for input (output driver in high-impedance state) or output.
XC167CI-16F Derivatives General Device Information Table 2 Symbol Pin Definitions and Functions (cont’d) Pin Num. PORT1 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 117 118 119 120 121 122 123 124 P1H.0 127 P1H.1 128 P1H.2 129 P1H.3 130 P1H.4 P1H.5 P1H.6 P1H.7 131 132 133 134 Data Sheet Input Outp. Function IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. Each pin can be programmed for input (output driver in high-impedance state) or output.
XC167CI-16F Derivatives General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function XTAL2 XTAL1 137 138 O I XTAL2: XTAL1: Output of the main oscillator amplifier circuit Input to the main oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.
XC167CI-16F Derivatives General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function VAREF VAGND VDDI 41 – Reference voltage for the A/D converter. 42 – Reference ground for the A/D converter. 48, 78, – 135 Digital Core Supply Voltage (On-Chip Modules): +2.5 V during normal operation and idle mode. Please refer to the Operating Conditions.
XC167CI-16F Derivatives Functional Description 3 Functional Description The architecture of the XC167 combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication).
XC167CI-16F Derivatives Functional Description 3.1 Memory Subsystem and Organization The memory space of the XC167 is configured in a Von Neumann architecture, which means that all internal and external resources, such as code memory, data memory, registers and I/O ports, are organized within the same linear address space. This common memory space includes 16 Mbytes and is arranged as 256 segments of 64 Kbytes each, where each segment consists of four data pages of 16 Kbytes each.
XC167CI-16F Derivatives Functional Description RH7) so-called General Purpose Registers (GPRs). The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR, any location in the DPRAM is bitaddressable. 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units.
XC167CI-16F Derivatives Functional Description 3.2 External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
XC167CI-16F Derivatives Functional Description The EBC also controls accesses to resources connected to the on-chip LXBus. The LXBus is an internal representation of the external bus and allows accessing integrated peripherals and modules in the same way as external components. The TwinCAN module is connected and accessed via the LXBus. Data Sheet 25 V1.
XC167CI-16F Derivatives Functional Description 3.3 Central Processing Unit (CPU) The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and accumulate unit (MAC), a register-file providing three register banks, and dedicated SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel shifter.
XC167CI-16F Derivatives Functional Description and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. Also multiplication and most MAC instructions execute in one single cycle. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: for example, a division algorithm is performed in 18 to 21 CPU cycles, depending on the data and division type.
XC167CI-16F Derivatives Functional Description 3.4 Interrupt System With an interrupt response time of typically 8 CPU clocks (in case of internal program execution), the XC167 is capable of reacting very fast to the occurrence of nondeterministic events. The architecture of the XC167 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.
XC167CI-16F Derivatives Functional Description Table 4 XC167 Interrupt Nodes Source of Interrupt or PEC Service Request Control Register Vector Location1) Trap Number CAPCOM Register 0 CC1_CC0IC xx’0040H 10H / 16D CAPCOM Register 1 CC1_CC1IC xx’0044H 11H / 17D CAPCOM Register 2 CC1_CC2IC xx’0048H 12H / 18D CAPCOM Register 3 CC1_CC3IC xx’004CH 13H / 19D CAPCOM Register 4 CC1_CC4IC xx’0050H 14H / 20D CAPCOM Register 5 CC1_CC5IC xx’0054H 15H / 21D CAPCOM Register 6 CC1_CC6IC xx’
XC167CI-16F Derivatives Functional Description Table 4 XC167 Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request Control Register Vector Location1) Trap Number CAPCOM Register 29 CC2_CC29IC xx’0110H 44H / 68D CAPCOM Register 30 CC2_CC30IC xx’0114H 45H / 69D CAPCOM Register 31 CC2_CC31IC xx’0118H 46H / 70D CAPCOM Timer 0 CC1_T0IC xx’0080H 20H / 32D CAPCOM Timer 1 CC1_T1IC xx’0084H 21H / 33D CAPCOM Timer 7 CC2_T7IC xx’00F4H 3DH / 61D CAPCOM Timer 8 CC2_T8IC xx’0
XC167CI-16F Derivatives Functional Description Table 4 XC167 Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request Control Register Vector Location1) Trap Number ASC1 Autobaud ASC1_ABIC xx’0108H 42H / 66D End of PEC Subchannel EOPIC xx’0130H 4CH / 76D CAPCOM6 Timer T12 CCU6_T12IC xx’0134H 4DH / 77D CAPCOM6 Timer T13 CCU6_T13IC xx’0138H 4EH / 78D CAPCOM6 Emergency CCU6_EIC xx’013CH 4FH / 79D CAPCOM6 CCU6_IC xx’0140H 50H / 80D SSC1 Transmit SSC1_TIC xx’0144H 51H
XC167CI-16F Derivatives Functional Description The XC167 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
XC167CI-16F Derivatives Functional Description 3.5 On-Chip Debug Support (OCDS) The On-Chip Debug Support system provides a broad range of debug and emulation features built into the XC167. The user software running on the XC167 can thus be debugged within the target system environment. The OCDS is controlled by an external debugging device via the debug interface, consisting of the IEEE-1149-conforming JTAG port and a break interface.
XC167CI-16F Derivatives Functional Description 3.6 Capture/Compare Units (CAPCOM1/2) The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered mode). The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events.
XC167CI-16F Derivatives Functional Description When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘captured’) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated.
XC167CI-16F Derivatives Functional Description Reload Reg. T0REL/T7REL f CC T0IN/T7IN T6OUF T0/T7 Input Control Timer T0/T7 CCxIO CCxIO CCxIRQ CCxIRQ Mode Control (Capture or Compare) Sixteen 16-bit Capture/ Compare Registers CCxIO f CC T6OUF T0IRQ, T7IRQ CCxIRQ T1/T8 Input Control Timer T1/T8 T1IRQ, T8IRQ Reload Reg. T1REL/T8REL CAPCOM1 provides channels x = 0 … 15, CAPCOM2 provides channels x = 16 … 31.
XC167CI-16F Derivatives Functional Description 3.7 The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one independent 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions (deadtime control).
XC167CI-16F Derivatives Functional Description 3.8 General Purpose Timer (GPT12E) Unit The GPT12E unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT12E unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2.
XC167CI-16F Derivatives Functional Description T3CON.BPS1 f GPT 2n:1 Basic Clock Interrupt Request (T2IRQ) Aux. Timer T2 T2IN T2EUD T2 Mode Control U/D Reload Capture Interrupt Request (T3IRQ) T3IN T3 Mode Control T3EUD Core Timer T3 T3OTL T3OUT Toggle Latch U/D Capture T4IN T4EUD T4 Mode Control Reload Aux.
XC167CI-16F Derivatives Functional Description count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT.
XC167CI-16F Derivatives Functional Description T6CON.BPS2 fGPT 2n:1 Basic Clock Interrupt Request (T5IRQ) GPT2 Timer T5 T5IN T5 Mode Control U/D Clear Capture CAPIN T3IN/ T3EUD CAPREL Mode Control GPT2 CAPREL Interrupt Request (CRIRQ) Reload Clear Interrupt Request (T6IRQ) Toggle FF T6IN T6 Mode Control GPT2 Timer T6 T6OTL T6OUT T6OUF U/D MCA05564 Figure 8 Data Sheet Block Diagram of GPT2 41 V1.
XC167CI-16F Derivatives Functional Description 3.9 Real Time Clock The Real Time Clock (RTC) module of the XC167 is directly clocked via a separate clock driver either with the on-chip auxiliary oscillator frequency (fRTC = fOSCa) or with the prescaled on-chip main oscillator frequency (fRTC = fOSCm/32). It is therefore independent from the selected clock generation mode of the XC167.
XC167CI-16F Derivatives Functional Description The RTC module can be used for different purposes: • • • • System clock to determine the current time and date, optionally during idle mode, sleep mode, and power down mode Cyclic time based interrupt, to provide a system time tick independent of CPU frequency and other resources, e.g. to wake up regularly from idle mode. 48-bit timer for long term measurements (maximum timespan is > 100 years).
XC167CI-16F Derivatives Functional Description 3.10 A/D Converter For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable (in two modes) and can thus be adjusted to the external circuitry.
XC167CI-16F Derivatives Functional Description 3.11 Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) The Asynchronous/Synchronous Serial Interfaces ASC0/ASC1 (USARTs) provide serial communication with other microcontrollers, processors, terminals or external peripheral components. They are upward compatible with the serial ports of the Infineon 8-bit microcontroller families and support full-duplex asynchronous communication and halfduplex synchronous communication.
XC167CI-16F Derivatives Functional Description 3.12 High Speed Synchronous Serial Channels (SSC0/SSC1) The High Speed Synchronous Serial Channels SSC0/SSC1 support full-duplex and halfduplex synchronous communication. It may be configured so it interfaces with serially linked peripheral components, full SPI functionality is supported. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.
XC167CI-16F Derivatives Functional Description 3.13 TwinCAN Module The integrated TwinCAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip TwinCAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.
XC167CI-16F Derivatives Functional Description Summary of Features • • • • • • • CAN functionality according to CAN specification V2.
XC167CI-16F Derivatives Functional Description 3.15 Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can be disabled until the EINIT instruction has been executed (compatible mode), or it can be disabled and enabled at any time by executing instructions DISWDT and ENWDT (enhanced mode).
XC167CI-16F Derivatives Functional Description 3.16 Clock Generation The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers to generate the clock signals for the XC167 with high flexibility. The master clock fMC is the reference clock signal, and is used for TwinCAN and is output to the external system. The CPU clock fCPU and the system clock fSYS are derived from the master clock either directly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC / 2). See also Section 4.4.1.
XC167CI-16F Derivatives Functional Description Table 7 Summary of the XC167’s Parallel Ports Port Control Alternate Functions PORT0 Pad drivers Address/Data lines or data lines1) PORT1 Pad drivers Address lines2) Capture inputs or compare outputs, Serial interface lines Port 2 Pad drivers, Open drain, Input threshold Capture inputs or compare outputs, Timer control signal, Fast external interrupt inputs Port 3 Pad drivers, Open drain, Input threshold Timer control signals, serial interface l
XC167CI-16F Derivatives Functional Description 3.18 Power Management The XC167 provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • • • Power Saving Modes switch the XC167 into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate.
XC167CI-16F Derivatives Functional Description 3.19 Instruction Set Summary Table 8 lists the instructions of the XC167 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “Instruction Set Manual”. This document also provides a detailed description of each instruction.
XC167CI-16F Derivatives Functional Description Table 8 Instruction Set Summary (cont’d) Mnemonic Description Bytes ROL/ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2 MOV(B) Move word (byte) data 2/4 MOVBS/Z Move byte operand to word op.
XC167CI-16F Derivatives Functional Description Table 8 Instruction Set Summary (cont’d) Mnemonic Description Bytes NOP Null operation 2 CoMUL/CoMAC Multiply (and accumulate) 4 CoADD/CoSUB Add/Subtract 4 Co(A)SHR (Arithmetic) Shift right 4 CoSHL Shift left 4 CoLOAD/STORE Load accumulator/Store MAC register 4 CoCMP Compare 4 CoMAX/MIN Maximum/Minimum 4 CoABS/CoRND Absolute value/Round accumulator 4 CoMOV Data move 4 CoNEG/NOP Negate accumulator/Null operation 4 Data Sheet
XC167CI-16F Derivatives Electrical Parameters 4 Electrical Parameters 4.1 General Parameters Table 9 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes Min. Max. TST TJ VDDI -65 150 °C 1) -40 150 °C under bias -0.5 3.25 V – Voltage on VDDP pins with respect to ground (VSS) VDDP -0.5 6.2 V – Voltage on any pin with respect to ground (VSS) VIN -0.
XC167CI-16F Derivatives Electrical Parameters Operating Conditions The following operating conditions must not be exceeded to ensure correct operation of the XC167. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 10 Operating Condition Parameters Parameter Symbol Limit Values Min. Max. Unit Notes Digital supply voltage for the core VDDI 2.35 2.7 V Active mode, fCPU = fCPUmax1)2) Digital supply voltage for IO pads VDDP 4.
XC167CI-16F Derivatives Electrical Parameters 6) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error current adds to the respective pin’s leakage current (IOZ). The amount of error current depends on the overload current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it.
XC167CI-16F Derivatives Electrical Parameters 4.2 Table 11 DC Parameters DC Characteristics (Operating Conditions apply)1) Parameter Symbol Limit Values Min. Max. Unit Test Condition Input low voltage TTL (all except XTAL1, XTAL3) VIL SR -0.5 0.2 × VDDP V - 0.1 – Input low voltage for XTAL1, XTAL32)3) VILC SR -0.5 0.3 × VDDI V – Input low voltage (Special Threshold) VILS SR -0.5 0.45 × V 4) Input high voltage TTL VIH (all except XTAL1, XTAL3) SR 0.2 × VDDP + 0.9 VDDP VDDP + 0.
XC167CI-16F Derivatives Electrical Parameters Table 11 DC Characteristics (Operating Conditions apply)1) (cont’d) Parameter Symbol Limit Values Unit Test Condition Min. Max. ICPDL11) ICPDH12) ILHI11) – 10 µA 120 – µA – -10 µA Level active hold current14) ILHA12) -100 – µA VIN = VILmax VIN = VIHmin VOUT = 0.5 × VDDP VOUT = 0.
XC167CI-16F Derivatives Electrical Parameters Table 12 Current Limits for Port Output Drivers Port Output Driver Mode Maximum Output Current (IOLmax, -IOHmax)1) Nominal Output Current (IOLnom, -IOHnom) Strong driver 10 mA 2.5 mA Medium driver 4.0 mA 1.0 mA Weak driver 0.5 mA 0.1 mA 1) An output current above |IOXnom| may be drawn from up to three pins at the same time.
XC167CI-16F Derivatives Electrical Parameters 4) The total supply current in Sleep and Power down mode is the sum of the temperature dependent leakage current and the frequency dependent current for RTC and main oscillator or auxiliary oscillator (if active). 5) This parameter is determined mainly by the transistor leakage currents. This current heavily depends on the junction temperature (see Figure 13).
XC167CI-16F Derivatives Electrical Parameters I [mA] IDDImax 140 120 IDDItyp 100 80 IIDXmax 60 IIDXtyp 40 20 10 Figure 11 Data Sheet 20 30 40 fCPU [MHz] Supply/Idle Current as a Function of Operating Frequency 63 V1.
XC167CI-16F Derivatives Electrical Parameters I [mA] 3.0 2.0 IPDMmax IPDMtyp 1.0 IPDAmax 0.1 32 kHz Figure 12 4 8 12 16 fOSC [MHz] Sleep and Power Down Supply Current due to RTC and Oscillator Running, as a Function of Oscillator Frequency IPDL [mA] 1.5 1.0 0.5 -50 Figure 13 Data Sheet 0 50 100 150 TJ [°C] Sleep and Power Down Leakage Supply Current as a Function of Temperature 64 V1.
XC167CI-16F Derivatives Electrical Parameters 4.3 Table 14 Analog/Digital Converter Parameters A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Min. Analog reference supply VAREF SR 4.5 Max. Unit Test Condition VDDP V 1) VSS + 0.1 VAREF V – V 2) 20 MHz 3) + 0.
XC167CI-16F Derivatives Electrical Parameters 3) The limit values for fBC must not be exceeded when selecting the peripheral frequency and the ADCTC setting. 4) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result (tSYS = 1/fSYS). Values for the basic clock tBC depend on programming and can be taken from Table 15. When the post-calibration is switched off, the conversion time is reduced by 12 × tBC.
XC167CI-16F Derivatives Electrical Parameters Sample time and conversion time of the XC167’s A/D Converter are programmable. In compatibility mode, the above timing can be calculated using Table 15. The limit values for fBC must not be exceeded when selecting ADCTC. Table 15 A/D Converter Computation Table1) ADCON.15|14 (ADCTC) A/D Converter Basic Clock fBC ADCON.
XC167CI-16F Derivatives Electrical Parameters 4.4 AC Parameters 4.4.1 Definition of Internal Timing The internal operation of the XC167 is controlled by the internal master clock fMC. The master clock signal fMC can be generated from the oscillator clock signal fOSC via different mechanisms. The duration of master clock periods (TCMs) and their variation (and also the derived external timing) depend on the used mechanism to generate fMC.
XC167CI-16F Derivatives Electrical Parameters The specification of the external timing (AC Characteristics) depends on the period of the CPU clock, called “TCP”. The other peripherals are supplied with the system clock signal fSYS which has the same frequency as the CPU clock signal fCPU.
XC167CI-16F Derivatives Electrical Parameters The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe. The VCO output clock is divided by the output prescaler (K = PLLODIV+1) to generate the master clock signal fMC. Therefore, the number of VCO cycles can be represented as K × N, where N is the number of consecutive fMC cycles (TCM). For a period of N × TCM the accumulated PLL jitter is defined by the deviation DN: DN [ns] = ±(1.5 + 6.
XC167CI-16F Derivatives Electrical Parameters Table 16 VCO Bands for PLL Operation1) PLLCON.PLLVB VCO Frequency Range Base Frequency Range 00 100 … 150 MHz 20 … 80 MHz 01 150 … 200 MHz 40 … 130 MHz 10 200 … 250 MHz 60 … 180 MHz 11 Reserved 1) Not subject to production test - verified by design/characterization. Data Sheet 71 V1.
XC167CI-16F Derivatives Electrical Parameters 4.4.2 On-chip Flash Operation The XC167’s Flash module delivers data within a fixed access time (see Table 17). Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles, where WS is the number of Flash access waitstates selected via bitfield WSFLASH in register IMBCTRL. The resulting duration of the access phase must cover the access time tACC of the Flash array.
XC167CI-16F Derivatives Electrical Parameters 4.4.3 Table 19 External Clock Drive XTAL1 External Clock Drive Characteristics (Operating Conditions apply) Parameter Symbol tOSC t1 t2 t3 t4 Oscillator period High time2) Low time2) Rise time2) Fall time2) Limit Values Unit Min. Max. SR 25 2501) ns SR 6 – ns SR 6 – ns SR – 8 ns SR – 8 ns 1) The maximum limit is only relevant for PLL operation to ensure the minimum input frequency for the PLL.
XC167CI-16F Derivatives Electrical Parameters 4.4.4 Testing Waveforms Output delay Output delay Hold time 2.0 V Hold time Input Signal (driven by tester) Output Signal (measured) 0.8 V 0.45 V Output timings refer to the rising edge of CLKOUT. Input timings are calculated from the time, when the input signal reaches VIH or VIL, respectively. MCD05556 Figure 18 Input Output Waveforms VLoad + 0.1 V Timing Reference Points V Load - 0.1 V V OH - 0.1 V V OL + 0.
XC167CI-16F Derivatives Electrical Parameters 4.4.5 External Bus Timing Table 20 CLKOUT Reference Signal Parameter Symbol Limits Min. tc5 tc6 tc7 tc8 tc9 CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time Unit Max. 40/30/251) CC ns CC 8 – ns CC 6 – ns CC – 4 ns CC – 4 ns 1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/33/40 MHz).
XC167CI-16F Derivatives Electrical Parameters Variable Memory Cycles External bus cycles of the XC167 are executed in five subsequent cycle phases (AB, C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx registers) to adapt the external bus cycles to the respective external module (memory, peripheral, etc.). The duration of the access phase can optionally be controlled by the external module via the READY handshake input.
XC167CI-16F Derivatives Electrical Parameters Table 22 External Bus Cycle Timing (Operating Conditions apply) Parameter Symbol Limits Min. Max.
XC167CI-16F Derivatives Electrical Parameters tp AB tpC tp D tp E tp F CLKOUT tc 21 tc 11 ALE tc 11/tc 14 A23-A16, BHE, CSx High Address tc 20 tc 10 RD WR(L/H) tc 31 tc 13 AD15-AD0 (read) AD15-AD0 (write) tc 23 Low Address tc 30 Data In tc 13 tc 15 Low Address tc 25 Data Out MCT05557 Figure 21 Data Sheet Multiplexed Bus Cycle 78 V1.
XC167CI-16F Derivatives Electrical Parameters tp AB tp C tp D tp E tp F CLKOUT tc 21 tc 11 ALE tc 11 /tc 14 A23-A0, BHE, CSx Address tc 20 tc 10 RD WR(L/H) tc 31 tc 30 D15-D0 (read) Data In tc 16 D15-D0 (write) tc 25 Data Out MCT05558 Figure 22 Data Sheet Demultiplexed Bus Cycle 79 V1.
XC167CI-16F Derivatives Electrical Parameters Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. The polarity of this input signal can be selected. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT.
XC167CI-16F Derivatives Electrical Parameters tpD tp E tpRDY tpF CLKOUT tc 10 tc 20 RD, WR tc 31 tc 30 D15-D0 (read) Data In tc 25 D15-D0 (write) Data Out tc31 READY Synchronous READY Asynchron.
XC167CI-16F Derivatives Electrical Parameters External Bus Arbitration Table 23 Bus Arbitration Timing (Operating Conditions apply) Parameter Symbol Limits Min. Max. Unit Input setup time for: HOLD input tc40 SR 24 – ns Output delay rising edge for: HLDA, BREQ tc41 CC 1 6 ns Output delay falling edge for: HLDA tc42 CC 1 10 ns Note: The shaded parameters have been verified by characterization. They are not subject to production test. Data Sheet 82 V1.
XC167CI-16F Derivatives Electrical Parameters CLKOUT tc 40 HOLD tc 42 HLDA BREQ 2) tc 10 /tc 14 CSx, RD, WR(L/H) 3) Addr, Data, BHE 1) Figure 24 MCT05560 External Bus Arbitration, Releasing the Bus Notes 1. The XC167 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to get active. 3. The control outputs will be resistive high (pull-up) after being driven inactive (ALE will be low). Data Sheet 83 V1.
XC167CI-16F Derivatives Electrical Parameters 3) CLKOUT tc 40 HOLD tc 41 HLDA tc 41 BREQ 1) tc 10 /tc 14 CSx, RD, WR(L/H) 2) tc 11/tc 12 /tc 13/tc 15 /tc 16 Addr, Data, BHE MCT05561 Figure 25 External Bus Arbitration, Regaining the Bus Notes 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the XC167 requesting the bus. 2.
XC167CI-16F Derivatives Package and Reliability 5 Package and Reliability 5.1 Packaging Table 24 Package Parameters Parameter Symbol Limit Values Unit Notes Min. Max. Thermal resistance junction to case RΘJC – 9 K/W – Thermal resistance junction to leads RΘJL – 41 K/W – Thermal resistance junction to case RΘJC – 7 K/W – Thermal resistance junction to leads RΘJL – 19 K/W – Green Package PG-TQFP-144-7 Standard Package P-TQFP-144-19 0.5 0.22 ±0.05 17.5 H 7˚ MAX. 0.15 +0.
XC167CI-16F Derivatives 0.5 0.22 ±0.05 2) 17.5 7˚ MAX. H 0.6 ±0.15 C 0.08 0.08 M A-B D C 144x 22 +0.08 0.12 -0.03 0.1 ±0.05 1.4 ±0.05 1.6 MAX. Package and Reliability 0.2 A-B D 144x 0.2 A-B D H 4x 20 1) D 22 B 20 1) A 144 1 Index Marking 1) 2) Does not include plastic or metal protrusion of 0.25 max. per side Does not include dambar protrusion of 0.08 max.
XC167CI-16F Derivatives Package and Reliability 5.2 Flash Memory Parameters The data retention time of the XC167’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 25 Flash Parameters (XC167, 128 Kbytes) Parameter Data retention time Symbol tRET Flash Erase Endurance NER Data Sheet Limit Values Unit Notes 103 erase/program cycles Min. Max.
w w w . i n f i n e o n .
