Datasheet

C161S
Timing Characteristics
Data Sheet 64 V1.0, 2003-11
Data hold after WR t
24
CC 15 + t
F
– TCL - 10
+
t
F
– ns
ALE rising edge after RD,
WR
t
26
CC -12 + t
F
– -12 + t
F
– ns
Address hold after WR
2)
t
28
CC 0 + t
F
– 0 + t
F
– ns
ALE falling edge to CS
3)
t
38
CC -8 - t
A
10 - t
A
-8 - t
A
10 - t
A
ns
CS
low to Valid Data In
3)
t
39
SR – 47 +
t
C
+ 2t
A
– 3TCL - 28
+
t
C
+ 2t
A
ns
CS
hold after RD, WR
3)
t
41
CC 9 + t
F
– TCL - 16
+
t
F
– ns
ALE falling edge to
RdCS
, WrCS (with
RW-delay)
t
42
CC 19 + t
A
– TCL - 6
+
t
A
– ns
ALE falling edge to
RdCS, WrCS (no
RW-delay)
t
43
CC -6 + t
A
– -6
+
t
A
– ns
RdCS
to Valid Data In
(with RW-delay)
t
46
SR – 20 + t
C
– 2TCL - 30
+
t
C
ns
RdCS to Valid Data In
(no RW-delay)
t
47
SR – 45 + t
C
– 3TCL - 30
+
t
C
ns
RdCS
, WrCS Low Time
(with RW-delay)
t
48
CC 38 + t
C
– 2TCL - 12
+
t
C
– ns
RdCS
, WrCS Low Time
(no RW-delay)
t
49
CC 63 + t
C
– 3TCL - 12
+
t
C
– ns
Data valid to WrCS
t
50
CC 28 + t
C
– 2TCL - 22
+
t
C
– ns
Data hold after RdCS
t
51
SR 0 – 0 – ns
Data float after RdCS
(with RW-delay)
1)
t
53
SR – 30 + t
F
– 2TCL - 20
+ 2
t
A
+ t
F
1)
ns
Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
t
A
+ t
C
+ t
F
(100 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
Min. Max. Min. Max.