Datasheet

C161S
Timing Characteristics
Data Sheet 54 V1.0, 2003-11
Data valid to WR t
22
CC 24 + t
C
– 2TCL - 26
+
t
C
– ns
Data hold after WR t
23
CC 36 + t
F
– 2TCL - 14
+
t
F
– ns
ALE rising edge after RD
,
WR
t
25
CC 36 + t
F
– 2TCL - 14
+
t
F
– ns
Address hold after RD
,
WR
t
27
CC 36 + t
F
– 2TCL - 14
+
t
F
– ns
ALE falling edge to CS
1)
t
38
CC -8 - t
A
10 - t
A
-8 - t
A
10 - t
A
ns
CS
low to Valid Data In
1)
t
39
SR – 47 + t
C
+ 2t
A
– 3TCL - 28
+
t
C
+ 2t
A
ns
CS
hold after RD, WR
1)
t
40
CC 57 + t
F
– 3TCL - 18
+
t
F
– ns
ALE fall. edge to RdCS
,
WrCS
(with RW delay)
t
42
CC 19 + t
A
– TCL - 6
+
t
A
– ns
ALE fall. edge to RdCS
,
WrCS
(no RW delay)
t
43
CC -6 + t
A
– -6
+
t
A
– ns
Address float after
RdCS
, WrCS (with RW
delay)
t
44
CC – 0 – 0ns
Address float after
RdCS, WrCS (no RW
delay)
t
45
CC – 25 – TCL ns
RdCS
to Valid Data In
(with RW delay)
t
46
SR – 20 + t
C
– 2TCL - 30
+
t
C
ns
RdCS
to Valid Data In
(no RW delay)
t
47
SR – 45 + t
C
– 3TCL - 30
+
t
C
ns
RdCS
, WrCS Low Time
(with RW delay)
t
48
CC 38 + t
C
– 2TCL - 12
+
t
C
– ns
RdCS
, WrCS Low Time
(no RW delay)
t
49
CC 63 + t
C
– 3TCL - 12
+
t
C
– ns
Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
t
A
+ t
C
+ t
F
(150 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
Min. Max. Min. Max.