Datasheet

C161S
Timing Characteristics
Data Sheet 53 V1.0, 2003-11
Table 17 Multiplexed Bus (Reduced Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
t
A
+ t
C
+ t
F
(150 ns at 20 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
Min. Max. Min. Max.
ALE high time
t
5
CC 11 + t
A
– TCL - 14
+
t
A
– ns
Address setup to ALE t
6
CC 5 + t
A
– TCL - 20
+
t
A
– ns
Address hold after ALE
t
7
CC 15 + t
A
– TCL - 10
+
t
A
– ns
ALE falling edge to RD
,
WR
(with RW-delay)
t
8
CC 15 + t
A
– TCL - 10
+
t
A
– ns
ALE falling edge to RD
,
WR
(no RW-delay)
t
9
CC -10 + t
A
– -10 + t
A
– ns
Address float after RD
,
WR
(with RW-delay)
t
10
CC – 6 – 6ns
Address float after RD
,
WR
(no RW-delay)
t
11
CC – 31 – TCL + 6 ns
RD
, WR low time
(with RW-delay)
t
12
CC 34 + t
C
– 2TCL - 16
+
t
C
– ns
RD
, WR low time
(no RW-delay)
t
13
CC 59 + t
C
– 3TCL - 16
+
t
C
– ns
RD to valid data in
(with RW-delay)
t
14
SR – 22 + t
C
– 2TCL - 28
+
t
C
ns
RD
to valid data in
(no RW-delay)
t
15
SR – 47 + t
C
– 3TCL - 28
+
t
C
ns
ALE low to valid data in
t
16
SR – 45 + t
A
+ t
C
– 3TCL - 30
+
t
A
+ t
C
ns
Address to valid data in
t
17
SR – 57 + 2t
A
+
t
C
– 4TCL - 43
+ 2
t
A
+ t
C
ns
Data hold after RD
rising edge
t
18
SR 0 – 0 – ns
Data float after RD
t
19
SR – 36 + t
F
– 2TCL - 14
+
t
F
ns