Datasheet

C161S
Timing Characteristics
Data Sheet 51 V1.0, 2003-11
RD, WR low time
(with RW-delay)
t
12
CC 30 + t
C
– 2TCL - 10
+
t
C
– ns
RD, WR low time
(no RW-delay)
t
13
CC 50 + t
C
– 3TCL - 10
+
t
C
– ns
RD
to valid data in
(with RW-delay)
t
14
SR – 20 + t
C
– 2TCL - 20
+
t
C
ns
RD
to valid data in
(no RW-delay)
t
15
SR – 40 + t
C
– 3TCL - 20
+
t
C
ns
ALE low to valid data in
t
16
SR – 40 + t
A
+ t
C
– 3TCL - 20
+
t
A
+ t
C
ns
Address to valid data in
t
17
SR – 50 + 2t
A
+ t
C
– 4TCL - 30
+ 2
t
A
+ t
C
ns
Data hold after RD
rising edge
t
18
SR 0 – 0 – ns
Data float after RD
t
19
SR – 26 + t
F
– 2TCL - 14
+
t
F
ns
Data valid to WR
t
22
CC 20 + t
C
– 2TCL - 20
+
t
C
– ns
Data hold after WR t
23
CC 26 + t
F
– 2TCL - 14
+
t
F
– ns
ALE rising edge after RD
,
WR
t
25
CC 26 + t
F
– 2TCL - 14
+
t
F
– ns
Address hold after RD
,
WR
t
27
CC 26 + t
F
– 2TCL - 14
+
t
F
– ns
ALE falling edge to CS
1)
t
38
CC -4 - t
A
10 - t
A
-4 - t
A
10 - t
A
ns
CS
low to Valid Data In
1)
t
39
SR – 40 + t
C
+ 2t
A
– 3TCL - 20
+
t
C
+ 2t
A
ns
CS
hold after RD, WR
1)
t
40
CC 46 + t
F
– 3TCL - 14
+
t
F
– ns
Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
t
A
+ t
C
+ t
F
(120 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
Min. Max. Min. Max.