Datasheet

C161S
Functional Description
Data Sheet 19 V1.0, 2003-11
Figure 5 Block Diagram of GPT1
With its maximum resolution of 8 TCL, the GPT2 module provides precise event control
and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU
clock. The count direction (up/down) for each timer is programmable by software.
Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5. The overflows/underflows of timer
T6 can cause a reload from the CAPREL register. The CAPREL register may capture
the contents of timer T5 based on an external signal transition on the corresponding port
pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This
allows the C161S to measure absolute time differences or to perform pulse multiplication
without software overhead.
T3
Mode
Control
2
n
: 1f
CPU
2
n
: 1f
CPU
T2
Mode
Control
GPT1 Timer T2
Reload
Capture
2
n
: 1f
CPU
T4
Mode
Control
GPT1 Timer T4
Reload
Capture
GPT1 Timer T3 T3OTL
U/D
T2EUD
T2IN
T3IN
T3EUD
T4IN
T4EUD
T3OUT
Toggle FF
U/D
U/D
Interrupt
Request
Interrupt
Request
Interrupt
Request
Other
Timers
MCT02141
n = 3 … 10