Datasheet

C161S
Functional Description
Data Sheet 10 V1.0, 2003-11
3 Functional Description
The architecture of the C161S combines advantages of both RISC and CISC processors
and of advanced peripheral subsystems in a very well-balanced way. In addition the on-
chip memory blocks allow the design of compact systems with maximum performance.
Figure 3 gives an overview of the different on-chip components and of the advanced,
high bandwidth internal bus structure of the C161S.
Note: All time specifications refer to a CPU clock of 20 MHz
(see definition in the AC Characteristics section).
Figure 3 Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).
C166-Core
CPU
Port 2
Interrupt Bus
XTAL
MCB04323_1S.vsd
Osc / PLL
RTC WDT
32
16
Interrupt Controller
16-Level
Priority
PEC
External Instr. / Data
GPT
T2
T3
T4
T5
T6
SSC
BRGen
(SPI)
ASC0
BRGen
(USART)
EBC
XBUS Control
External Bus
Control
IRAM
Dual Port
Internal
RAM
2 Kbytes
ProgMem
Internal
ROM
Area
Data
Data
16
16
16
Instr. / Data
Port 0
Port 6
6
4
Port 1
16
216
Port 5Port 3
12
Port 4
7
Peripheral Data Bus
16
On-Chip XBUS (16-Bit Demux)