D a t a S h e e t , V 1. 0 , N o v . 20 0 3 C161S 1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er M i c r o c o n t r o l l er s N e v e r s t o p t h i n k i n g .
Edition 2003-11 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved.
D a t a S h e e t , V 1. 0 , N o v . 20 0 3 C161S 1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er M i c r o c o n t r o l l er s N e v e r s t o p t h i n k i n g .
C161S Revision History: 2003-11 Previous Version: none Page V1.0 Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Template: mc_tmplt_a5.
16-Bit Single-Chip Microcontroller C166 Family C161S C161S 1 • • • • • • • • • • • • • • Summary of Features High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 Mbytes
C161S Summary of Features This document describes several derivatives of the C161 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 C161S Derivative Synopsis Derivative Max. Operating Frequency Operating Voltage Ambient Temperature SAB-C161S-L25M 25 MHz 4.5 to 5.5 V (Standard) 0 to 70 °C SAF-C161S-L25M 25 MHz 4.5 to 5.
C161S General Device Information 2 General Device Information 2.1 Introduction The C161S is a derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides clock generation via PLL and power management features. The C161S is especially suited for cost sensitive applications.
C161S General Device Information VDD VSS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 C161S P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.0/AD8 P0H.1/AD9 VSS VDD P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P4.0/A16 P4.1/A17 P4.2/A18 P4.
C161S General Device Information Table 2 Pin Definitions and Functions Symbol Pin No. Input Function Outp. XTAL1 2 I XTAL2 3 O P3 IO P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 5 6 7 8 9 10 11 12 13 14 15 P3.13 16 P4 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 Data Sheet I O I I I I I/O I/O O I/O O O I/O IO 17 18 19 20 23 24 O O O O O O XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit.
C161S General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Function Outp. RD 25 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/ WRL 26 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
C161S General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Function Outp. PORT1 P1L.0-7 IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.
C161S General Device Information Table 2 Pin Definitions and Functions (cont’d) Symbol Pin No. Input Function Outp. P6 IO P6.0 P6.1 P6.2 P6.3 68 69 70 71 IO P2 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 O O O O 72 73 74 75 76 77 78 P5 I I I I I I I I P5.14 P5.15 79 80 I I VDD 4, 22, 37, 64 – Port 6 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state.
C161S General Device Information Note: The following behavioural differences must be observed when the bidirectional reset is active: • • • • • Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. The reset indication flags always indicate a long hardware reset. The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low.
C161S Functional Description 3 Functional Description The architecture of the C161S combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the onchip memory blocks allow the design of compact systems with maximum performance. Figure 3 gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161S. C166-Core ProgMem 16 Data 32 Internal ROM Area CPU Instr.
C161S Functional Description 3.1 Memory Organization The memory space of the C161S is configured in a von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 Mbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.
C161S Functional Description 3.2 External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC).
C161S Functional Description 3.3 Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161S’s instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock.
C161S Functional Description A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.
C161S Functional Description 3.3.1 Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161S is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C161S supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller.
C161S Functional Description Table 3 C161S Interrupt Nodes Source of Interrupt or Request PEC Service Request Flag Enable Flag Interrupt Vector Vector Location Trap Number Unassigned node CC8IR CC8IE CC8INT 00’0060H 18H External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H 19H External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H 1AH External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH 1BH External Interrupt 4 CC12IR CC12IE CC12INT 00’0070H 1CH External Interrupt 5 CC13IR CC13
C161S Functional Description The C161S also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
C161S Functional Description 3.4 General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2.
C161S Functional Description U/D T2EUD fCPU 2n : 1 T2IN Interrupt Request GPT1 Timer T2 T2 Mode Control Reload Capture fCPU Interrupt Request n 2 :1 Toggle FF T3 Mode Control T3IN GPT1 Timer T3 T3OTL T3OUT U/D T3EUD Other Timers Capture Reload T4IN fCPU 2n : 1 T4 Mode Control GPT1 Timer T4 Interrupt Request U/D T4EUD MCT02141 n = 3 … 10 Figure 5 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement.
C161S Functional Description The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. fSYS 2n : 1 Interrupt Request (T5IR) GPT2 Timer T5 T5 Mode Control U/D Clear Capture GPT2 CAPREL T3IN/ Interrupt Request (CRIR) MUX CAPIN Interrupt Request (T6IR) CT3 Clear fSYS 2n : 1 GPT2 Timer T6 T6 Mode Control Toggle FF T6OTL U/D Mcb03999_x1s.
C161S Functional Description 3.5 Real Time Clock The Real Time Clock (RTC) module of the C161S consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32) and is therefore independent from the selected clock generation mode of the C161S. All timers count up.
C161S Functional Description 3.6 Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
C161S Functional Description 3.7 Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored.
C161S Functional Description 3.9 Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock.
C161S Functional Description 3.10 Power Management The C161S provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • • • Power Saving Modes switch the C161S into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Power Down Mode stops all clock signals and all operation (RTC may optionally continue running).
C161S Functional Description 3.11 Instruction Set Summary Table 5 lists the instructions of the C161S in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailed description of each instruction.
C161S Functional Description Table 5 Instruction Set Summary (cont’d) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Data Sheet Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand with zero extension Jump absolute/indirect/relative if condition is met Bytes 2/4 2/4 2/4 4 Jump ab
C161S Functional Description 3.12 Special Function Registers Overview Table 6 lists all SFRs which are implemented in the C161S in alphabetical order. The following markings assist in classifying the listed registers: “b” in the “Name” column marks Bit-addressable SFRs. “E” in the “Physical Address” column marks (E)SFRs in the Extended SFR-Space. “X” in the “Physical Address” column marks registers within on-chip X-peripherals. Table 6 Name C161S Registers, Ordered by Name 8-Bit Description Addr.
C161S Functional Description Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr. Reset Value CP FE10H 08H CPU Context Pointer Register FC00H b FF6AH B5H GPT2 CAPREL Interrupt Ctrl. Reg. 0000H FE08H 04H CPU Code Seg. Pointer Reg.
C161S Functional Description Table 6 Name C161S Registers, Ordered by Name (cont’d) Physical Address 8-Bit Description Addr. Reset Value P0L b FF00H 80H Port 0 Low Reg. (Lower half of PORT0) 00H P1H b FF06H 83H Port 1 High Reg. (Upper half of PORT1) 00H P1L b FF04H 82H Port 1 Low Reg.
C161S Functional Description Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Description Addr.
C161S Functional Description Table 6 Name C161S Registers, Ordered by Name (cont’d) 8-Bit Description Addr.
C161S Electrical Parameters 4 Electrical Parameters 4.1 Absolute Maximum Ratings Table 7 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes Min. Max. TST TJ VDD -65 150 °C – -40 150 °C under bias -0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 VDD + 0.
C161S Electrical Parameters 4.2 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C161S. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.
C161S Electrical Parameters 4.3 Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161S and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C161S will provide signals with the respective timing characteristics.
C161S Electrical Parameters 4.4 Table 9 DC Parameters DC Characteristics (Standard Supply Voltage Range) (Operating Conditions apply)1) Parameter Symbol Limit Values Min. Unit Test Condition Max. Input low voltage (TTL, all except XTAL1) VIL 0.2 VDD V - 0.1 – Input low voltage XTAL1 VIL2 SR -0.5 0.3 VDD V VIH SR 0.2 VDD VDD + V – Input high voltage (TTL, all except RSTIN and XTAL1) SR -0.5 + 0.9 – 0.5 Input high voltage RSTIN (when operated as input) VIH1 SR 0.
C161S Electrical Parameters Table 9 DC Characteristics (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply)1) Parameter Symbol Limit Values Min. 7) Port 6 active current PORT0 configuration current7) XTAL1 input current Pin capacitance8) (digital inputs/outputs) 6) IP6L -500 IP0H5) – IP0L6) -100 IIL CC – CIO CC – Unit Test Condition Max.
C161S Electrical Parameters Table 10 DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply)1) Parameter Symbol Limit Values Min. Input low voltage (TTL, all except XTAL1) VIL Input low voltage XTAL1 VIL2 SR -0.5 VIH SR 1.8 Input high voltage (TTL, all except RSTIN and XTAL1) SR -0.5 Unit Test Condition Max. 0.8 V – 0.3 VDD V – VDD + V – V – V – 0.5 Input high voltage RSTIN (when operated as input) VIH1 SR 0.6 VDD VDD + Input high voltage XTAL1 VIH2 SR 0.
C161S Electrical Parameters Table 10 DC Characteristics (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply)1) Parameter Symbol Limit Values Min. PORT0 configuration current 7) XTAL1 input current Pin capacitance8) (digital inputs/outputs) 5) IP0H – IP0L6) -100 IIL CC – CIO CC – Unit Test Condition Max.
C161S Electrical Parameters Table 11 Power Consumption C161S (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Limit Values Min. Max. Unit Test Condition Power supply current (active) with all peripherals active IDD5 – 15 + mA 1.8 × fCPU RSTIN = VIL2 fCPU in [MHz]1) Idle mode supply current with all peripherals active IIDX5 – 3+ mA 0.
C161S Electrical Parameters Table 12 Power Consumption C161S (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Symbol Limit Values Min. Max. Unit Test Condition Power supply current (active) with all peripherals active IDD3 – 7+ mA 1.2 × fCPU RSTIN = VIL2 fCPU in [MHz]1) Idle mode supply current with all peripherals active IIDX3 – 1+ mA 0.
C161S Electrical Parameters I [mA] IDD5max 100 IDD5typ 80 IDD3max 60 IDD3typ 40 IIDX5max IIDX5typ 20 IIDX3max IIDX3typ 10 Figure 8 Data Sheet 20 30 40 fCPU [MHz] Supply and Idle Current as a Function of Operating Frequency 42 V1.
C161S Electrical Parameters I [µA] 3000 IIDO5max 2500 IIDO5typ IIDO3max IIDO3typ IPDR5max 1500 1000 IPDR3max 500 IPDOmax 10 Figure 9 Data Sheet 20 30 40 fOSC [MHz] Sleep and Power Down Supply Current as a Function of Oscillator Frequency 43 V1.
C161S Timing Characteristics 5 Timing Characteristics 5.1 Definition of Internal Timing The internal operation of the C161S is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).
C161S Timing Characteristics levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins P0.15-13 (P0H.7-5). Table 13 associates the combinations of these three bits with the respective clock generation mode. Table 13 C161S Clock Generation Modes CLKCFG (P0H.7-5) CPU Frequency External Clock fCPU = fOSC × F Input Range1) Notes 111 fOSC × 4 fOSC × 3 fOSC × 2 fOSC × 5 fOSC × 1 fOSC × 1.5 fOSC / 2 fOSC × 2.5 2.5 to 6.25 MHz Default configuration 3.33 to 8.
C161S Timing Characteristics The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and Figure 11).
C161S Timing Characteristics Direct Drive When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC.
C161S Timing Characteristics 5.2 External Clock Drive XTAL1 Table 14 Parameter External Clock Drive XTAL1 (Operating Conditions apply) Symbol Direct Drive 1:1 Min. Max. Min. Max. – 20 – 601) 5001) ns SR 203) – 5 – 10 – ns SR 203) – 5 – 10 – ns SR – 8 – 5 – 10 ns SR – 8 – 5 – 10 ns High time2) t1 t2 t3 t4 2) Fall time Unit Min. tOSC SR 40 Rise time2) PLL 1:N Max.
C161S Timing Characteristics 5.3 Testing Waveforms 2.4 V 1.8 V 1.8 V Test Points 0.8 V ’ 0.8 V 0.45 V ’ ’ AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at VIH min for a logic 1’ and VIL max for a logic 0’. ’ MCA04414 Figure 13 Input Output Waveforms VLoad + 0.1 V VOH - 0.1 V Timing Reference Points VLoad - 0.1 V VOL + 0.
C161S Timing Characteristics Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. Table 15 describes, how these variables are to be computed.
C161S Timing Characteristics Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. Max. Min. Max.
C161S Timing Characteristics Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. Max. Min. Max. ALE fall. edge to RdCS, WrCS (with RW delay) t42 CC 16 + tA – TCL - 4 + tA – ns ALE fall.
C161S Timing Characteristics Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Max. Min. Max.
C161S Timing Characteristics Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Max. Min. Max.
C161S Timing Characteristics Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Max. Min. Max.
C161S Timing Characteristics t5 t16 t25 ALE t38 t39 t40 CSxL t17 A23-A16 (A15-A8) BHE, CSxE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t8 Data In t10 t14 RD t42 t44 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address t8 WR, WRL, WRH t42 Data Out t56 t10 t22 t12 t44 t50 WrCSx t48 Figure 15 Data Sheet External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE 56 V1.
C161S Timing Characteristics t5 t16 t25 t39 t40 t17 t27 ALE t38 CSxL A23-A16 (A15-A8) BHE, CSxE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t10 t8 t14 RD t44 t42 t12 t51 t52 t46 RdCSx t48 Write Cycle BUS t23 Address Data Out t8 WR, WRL, WRH t56 t10 t44 t42 t22 t12 t50 WrCSx t48 Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet 57 V1.
C161S Timing Characteristics t5 t16 t25 ALE t38 t39 t40 CSxL t17 A23-A16 (A15-A8) BHE, CSxE t27 Address t6 t7 t54 t19 Read Cycle BUS t18 Address t9 Data In t11 t15 RD t43 t13 t45 t51 t52 t47 RdCSx t49 Write Cycle BUS t23 Address t9 WR, WRL, WRH t43 Data Out t56 t11 t22 t45 t13 t50 WrCSx t49 Figure 17 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE 58 V1.
C161S Timing Characteristics t5 t16 t25 t39 t40 t17 t27 ALE t38 CSxL A23-A16 (A15-A8) BHE, CSxE Address t6 t7 t54 t19 Read Cycle BUS t18 Address Data In t9 t11 RD t15 t13 t43 t45 RdCSx t51 t52 t47 t49 Write Cycle BUS t23 Address Data Out t56 t9 WR, WRL, WRH t11 t22 t13 t43 t45 t50 WrCSx t49 Figure 18 Data Sheet External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE 59 V1.
C161S Timing Characteristics Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. Max. Min. Max.
C161S Timing Characteristics Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. Data hold after WR t24 CC 10 + tF Max. Min. Max.
C161S Timing Characteristics Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz Min. Max. Min. Max.
C161S Timing Characteristics Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Max. Min. Max.
C161S Timing Characteristics Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Data hold after WR t24 CC 15 + tF Max. Min. Max.
C161S Timing Characteristics Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 20 MHz 1 / 2TCL = 1 to 20 MHz Min. Max. Min. Max.
C161S Timing Characteristics t5 t16 t26 ALE t38 t39 t41 CSxL t17 A23-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t20 t18 Read Cycle BUS (D15-D8) D7-D0 Data In t8 t14 RD t12 t42 RdCSx t51 t53 t46 t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t22 t12 t42 t50 WrCSx t48 Figure 19 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE 66 V1.
C161S Timing Characteristics t5 t16 t26 ALE t38 t39 t41 CSxL t17 A23-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t20 Read Cycle BUS (D15-D8) D7-D0 t18 Data In t8 t14 RD t12 t42 t51 t53 t46 RdCSx t48 Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH t24 Data Out t57 t8 t22 t12 t42 t50 WrCSx t48 Figure 20 Data Sheet External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE 67 V1.
C161S Timing Characteristics t5 t16 t26 ALE t38 t39 t41 CSxL t17 A23-A16 A15-A0 BHE, CSxE t28 Address t6 Read Cycle BUS (D15-D8) D7-D0 t55 t21 t18 Data In t9 t15 RD t43 t13 t51 t68 t47 RdCSx t49 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t57 t9 t22 WR, WRL, WRH t13 t50 t43 WrCSx t49 Figure 21 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet 68 V1.
C161S Timing Characteristics t5 t16 t26 ALE t38 t39 t41 CSxL t17 A23-A16 A15-A0 BHE, CSxE t28 Address t6 t55 t21 Read Cycle BUS (D15-D8) D7-D0 t18 Data In t9 t15 RD t13 t43 t51 t68 t47 RdCSx t49 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t57 t9 t22 WR, WRL, WRH t13 t43 t50 WrCSx t49 Figure 22 Data Sheet External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE 69 V1.
C161S Package Outlines 0.88 ±0.15 C 12.35 7˚ MAX. H 0.65 0.3 ±0.08 0.15 +0.08 -0.02 2.45 MAX. 2 +0.1 -0.05 Package Outlines 0.25 MIN. 6 0.1 0.12 M A-B D C 80x 17.2 0.2 A-B D 4x 14 1) 0.2 A-B D H 4x D 14 1) 17.2 B A 80 Index Marking 1) 1 0.6 x 45˚ Does not include plastic or metal protrusion of 0.25 max.
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